If 'clk_hw_register()' fails, it is likely that we expect to return an
error instead of a valid pointer (which would mean success).

Fix commit f5644f10 ("clk: at91: Migrate to clk_hw based registration
and OF APIs")
Signed-off-by: NChristophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

I made a mistake as for naming for this block.  The MIO block is not
implemented for these 3 SoCs in the first place.  The current naming
will be a trouble if an SoC with both MIO and SD-ctrl blocks appear
in the future.

This driver has just been merged in the previous merge window.
Rename it before the release.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The first loop of this "for" statement writes memory beyond the
allocated clk_hw_onecell_data.

It should be:
    for (clk_num--; clk_num >= 0; clk_num--)
            ...

Or more simply:
    while (--clk_num >= 0)
            ...

Fixes: 734d82f4 ("clk: uniphier: add core support code for UniPhier clock driver")
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but
also reset controller.  It worked fine that single sysctrl/mediactrl
device node in DT can be used to initialize clock driver and populate
platform device for reset controller.  But it stops working after
commit 989eafd0 ("clk: core: Avoid double initialization of clocks")
gets merged.  The commit sets flag OF_POPULATED during clock
initialization to skip the platform device populating for the same
device node.  On hi6220, it effectively makes hi6220-sysctrl reset
driver not probe any more.

The patch changes hi6220 sysctrl and mediactrl clock init macro from
CLK_OF_DECLARE to CLK_OF_DECLARE_DRIVER, so that the reset driver using
the same hardware block can continue working.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Tested-by: NJohn Stultz <john.stultz@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

For the gate part of the peripheral clock setting the bit disables the
clock and clearing it enables the clock. This is not the default behavior
of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Fixes: 8ca4746a ("clk: mvebu: Add the peripheral clock driver for Armada 3700")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Fixes setting low-resolution video modes on HDMI.  Now the PLLH_PIX
divider adjusts itself until the PLLH is within bounds.
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The commit 9b4cac33 ("clk: max77686: Migrate to clk_hw based OF and
registration APIs") converted the driver to use the new provider API to
register clocks using clk_hw.

But unfortunately, in the conversion it missed to set the num_clks value
which lead to the following error when trying to register a clk provider:

[    1.963782] of_clk_max77686_get: invalid index 0
[    1.967460] ERROR: could not get clock /rtc@10070000:rtc_src(1)
[    1.973638] s3c-rtc 10070000.rtc: failed to find rtc source clock

Fix it by correctly set the max77686_clk_driver_data num_clks member.

Fixes: 9b4cac33 ("clk: max77686: Migrate to clk_hw based OF and registration APIs")
Reported-by: NMarkus Reichl <m.reichl@fivetechno.de>
Suggested-by: NTobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: NMarkus Reichl <m.reichl@fivetechno.de>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

While trying using a peripheral clock on a driver, I saw that the clock
pointer returned by the provider was NULL.

The problem was a missing indirection. It was the pointer stored in the
hws array which needed to be updated not the value it contains.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Fixes: 8ca4746a ("clk: mvebu: Add the peripheral clock driver for Armada 3700")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Only propose the mediatek clock drivers on this platform, unless
build-testing.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: Shunli Wang <shunli.wang@mediatek.com>
Cc: James Liao <jamesjj.liao@mediatek.com>
Cc: Erin Lo <erin.lo@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

If the driver is built as a module, autoload won't work because the module
alias information is not filled. So user-space can't match the registered
device with the corresponding module.

Export the module alias information using the MODULE_DEVICE_TABLE() macro.

Before this patch:

$ modinfo drivers/clk/samsung/clk-exynos-audss.ko | grep alias
alias:          platform:exynos-audss-clk

After this patch:

$ modinfo drivers/clk/samsung/clk-exynos-audss.ko | grep alias
alias:          platform:exynos-audss-clk
alias:          of:N*T*Csamsung,exynos5420-audss-clockC*
alias:          of:N*T*Csamsung,exynos5420-audss-clock
alias:          of:N*T*Csamsung,exynos5410-audss-clockC*
alias:          of:N*T*Csamsung,exynos5410-audss-clock
alias:          of:N*T*Csamsung,exynos5250-audss-clockC*
alias:          of:N*T*Csamsung,exynos5250-audss-clock
alias:          of:N*T*Csamsung,exynos4210-audss-clockC*
alias:          of:N*T*Csamsung,exynos4210-audss-clock

Fixes: 4d252fd5 ("clk: samsung: Allow modular build of the Audio Subsystem CLKCON driver")
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org>
Tested-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The 3rd argument of regmap_read() takes a pointer to unsigned int.
This driver is saved just because u32 happens to be typedef'ed as
unsigned int, but we should not rely on that fact.  Change the
variable type just in case.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

I do not know why, but I missed to add this compatible string in
the initial commit of this driver.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds clock support to Loongson1C SoC.
Signed-off-by: NYang Ling <gnaygnil@gmail.com>
Acked-by: NKeguang Zhang <keguang.zhang@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Make use of GENMASK instead of open coding the equivalent operation,
and update the PLL formula.
Signed-off-by: NKelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch updates some clock names of Loongson1B,
and adds AC97, DMA and NAND clock.
Signed-off-by: NKelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Factor out the common functions into loongson1/clk.c
to support both Loongson1B and Loongson1C. And, put
the rest into loongson1/clk-loongson1b.c.
Signed-off-by: NKelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Clock driver should be registered with an earlier initcall than
module_init which is used by most of client device drivers.  Otherwise,
probing of these client drivers will likely be deferred due to that
calls into clk API will return -EPROBE_DEFER.

Deferred probing is not a problem for most subsystems, but could bring
some side effect for particular subsystem, like display.  On ZX296718
platform, we get Linux logo and boot log lost from display device, just
because the DRM/KMS driver gets -EPROBE_DEFER from devm_clk_get() call.

Let's use core_initcall (qcom and a few other clk drivers use that) for
driver registration to avoid those unnecessary -EPROBE_DEFER and get rid
of the side effect with ZX296718 display system.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Original commit, which added support for Armada CP110 system controller
used global variables for storing all clock information. It worked
fine for Armada 7k SoC, with single CP110 block. After dual-CP110 Armada 8k
was introduced, the data got overwritten and corrupted.

This patch fixes the issue by allocating resources dynamically in the
driver probe and storing it as platform drvdata.

Fixes: d3da3eae ("clk: mvebu: new driver for Armada CP110 system ...")
Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
CC: <stable@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Armada CP110 system controller comprises its own routine responsble
for registering gate clocks. Among others 'flags' field in
struct clk_init_data was not set, using a random values, which
may cause an unpredicted behavior.

This patch fixes the problem by resetting all fields of clk_init_data
before assigning values for all gated clocks of Armada 7k/8k SoCs family.

Fixes: d3da3eae ("clk: mvebu: new driver for Armada CP110 system ...")
Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
CC: <stable@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Free memory mapping, if lpc32xx_clk_init is not successful.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: NVladimir Zapolskiy <vz@mleia.com>
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Referring to the u-boot sources for the Netgear WNR854T, add support
for the mv88f5181.

[gregory.clement@free-electrons.com: fix commit title]
Signed-off-by: NJamie Lentin <jm@lentin.co.uk>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Free memory mapping if init is not successful.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Reviewed-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

There's been a copy and paste mistake in the A23 and A33 from the H3,
leading in the reset offset for the UART and I2C.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Assume that if the oscillator is enabled (OSC32EN bit is present), the
delay has already elapsed as the bootloader probably waited for the
oscillator to settle. This could waste up to 1.2s.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Starting with sama5d4, the crystal oscillator is always enabled at startup
and the SCKC doesn't have an OSC32EN bit anymore.

Add support for that new controller.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Move all clocks related to the slow clock controller to sckc.c. This avoids
extern definitions and allows to remove sckc.h
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
[sboyd@codeaurora.org: Mark some functions static]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Initialize the GPU clock muxes to sane inputs. Until now they have
not been changed from their default values, which means that both
GPU3D shader and GPU2D core were fed by clock inputs whose rates
exceed the maximium allowed frequency of the cores by as much as
200MHz.

This fixes a severe GPU stability issue on i.MX6DL.

Cc: stable@vger.kernel.org
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The current clock tree only implements the minimal set of differences
between the i.MX6Q and the i.MX6DL, but that doesn't really reflect
reality.

Apply the following fixes to match the RM:
- DL has no GPU3D_SHADER_SEL/PODF, the shader domain is clocked by
  GPU3D_CORE
- GPU3D_SHADER_SEL/PODF has been repurposed as GPU2D_CORE_SEL/PODF
- GPU2D_CORE_SEL/PODF has been repurposed as MLB_SEL/PODF

Cc: stable@vger.kernel.org
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add clocks configuration for CSI, FIRI and IEEE1588.
Signed-off-by: NFabien Lahoudere <fabien.lahoudere@collabora.co.uk>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add clock data arrays for all UniPhier SoCs with a binding document.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This includes UniPhier clock driver code, except SoC-specific
data arrays.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This clock is present on BCM53573 devices (including BCM47189) that use
Cortex-A7. ILP is a part of PMU (Power Management Unit) multi-function
device so we use syscon (and regmap) for it.
Signed-off-by: NRafał Miłecki <rafal@milecki.pl>
Acked-by: NRob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Remove 0 from clk_init_data to silence sparse]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Adding missing reset lines for USB 3.0 PHY.
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The zx296718 clock driver has a creative way of assigning the register
values for each clock, by initializing an __iomem pointer to an
offset and then later adding the base (from ioremap) on top
with a cast to u64. This fail on all 32-bit architectures during
compile testing:

drivers/clk/zte/clk-zx296718.c: In function 'top_clocks_init':
drivers/clk/zte/clk-zx296718.c:554:35: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
   zx296718_pll_clk[i].reg_base += (u64)reg_base;
drivers/clk/zte/clk-zx296718.c:579:29: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
drivers/clk/zte/clk-zx296718.c:592:31: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]

It would be nice to avoid all the casts, but I decided to simply
shut up the warnings by changing the type from u64 to uintptr_t,
which does the right thing in practice.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: ca023328 ("clk: zx: register ZX296718 clocks")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kmalloc_array".

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use the builtin_platform_driver() macro to make the code simpler.
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The register offset for the mipi-csi clk is off by 4, a copy paste
error from the mipi-dsi clk.

Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The PLLs have a "lock" bit in their configuration registers which
indicate if the PLL has locked on to the requested clock rate. We
check this bit in the .set_rate op. The PLL cannot lock on if it's
not running, which might be a false positive (warning).

Set the CLK_SET_RATE_UNGATE flag for all PLLs so whenever clk_set_rate
is called on them, they get enabled and the "lock" check is really
checking the PLL.

Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The LCD controller and HDMI controller use the LCDx-CHy and HDMI clocks
to generate their dot clocks. To be able to generate a full range of
possible clock rates, the parent PLL clock rates should also be changed.

Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch configures the semi-synchronous mode of the video clocks
of clkgenD2.
Signed-off-by: NOlivier Bideau <olivier.bideau@st.com>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>