Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

As of commit 40461472 ("Update FSL
esdhc binding"), we use "fsl,esdhc" compatible entry as a base
match. U-Boot will use the same compatible to fixup esdhc nodes.

This patch updates 83xx dts files so that they conform to the new
bindings.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The current device tree for the MPC8272ADS assumes a mapping of 32 MB
of NOR flash at 0xFE00.0000, while there are actually only 8 MB on
the boards, mapped at 0xFF80.0000. When booting an uImage with such a
device tree, the kernel crashes because 0xFE00.0000 is not mapped.

Also introduce aliases for serial[01] and ethernet[01].
Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

As subject says, add dts files for Xilinx ML510 reference design with
the PCI host bridge device.
Signed-off-by: NRoderick Colenbrander <thunderbird2k@gmail.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Now that the 4xx NAND driver is available again in arch/powerpc, let's
enable it on Sequoia. This patch also disables the early debug messages
(CONFIG_PPC_EARLY_DEBUG) in the Sequoia defconfig.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Now that leds-gpio is a proper OF platform driver, the Warp can use
the leds-gpio driver rather than the old out-of-kernel driver.

One side-effect is the leds-gpio driver always turns the leds off
while the old driver left them alone. So we have to set them back to
the correct settings.
Signed-off-by: NSean MacLennan <smaclennan@pikatech.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

The P2020 is a dual e500v2 core based SOC with:
* 3 PCIe controllers
* 2 General purpose DMA controllers
* 2 sRIO controllers
* 3 eTSECS
* USB 2.0
* SDHC
* SPI, I2C, DUART
* enhanced localbus
* and optional Security (P2020E) security w/XOR acceleration

The p2020 DS reference board is pretty similar to the existing MPC85xx
DS boards and has a ULI 1575 connected on one of the PCIe controllers.
Signed-off-by: NTed Peters <Ted.Peters@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

In these configuration we expect to have large amounts of memory (> 4G)
and thus will bounce via swiotlb some region of PCI address space.

The outbound windows were wasting 512M of address space by leaving a
gap between the top of the outbound window and the 4G boundary.  By
moving the top of the outbound window up to the 4G boundary we can
reclaim the vast majority of the 512M (minus space needed for PEXCSRBAR)
and thus reduces the amount of memory we have to bounce.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The MPC8568/9 chips support MSIs on PCIe so no reason not to enable them.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

For serial flash support we need to:

- Add QE Par IO Bank E device tree node, a GPIO from this bank is
  used for SPI chip-select line;
- Add serial-flash node;
- Add proper module alias into of/base.c.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Select HAS_RAPIDIO symbol and add rio nodes for MPC8568E-MDS
and MPC8569E-MDS boards.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Note that eSDHC and DUART0 are mutually exclusive on MPC8569E-MDS
boards. Default option is DUART0, so eSDHC is disabled by default.
U-Boot will fixup device tree if eSDHC should be used instead of
DUART0.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch fixes bogus reg = <> property in the localbus node,
and fixes interrupt property (should be "interrupts").

Also add node for NAND support.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

fsl,exec-units-mask should be 0xbfe to include SNOW unit in
MPC8569E's security engine.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level.  It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add fsl,qe-num-riscs and fsl,qe-num-snums to all the devices trees which
have qe node.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The MPC8569 is similiar to the MPC8568.  It doubles the number of
QUICC Engine RISC cores from 2 to 4.  Removes eTSECs, TLU and adds
the eSDHC controller.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The new dts places most of the devices in physical address space
above 32-bits, which allows us to have more than 4GB of RAM present.
Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The cell-index property isn't used on PCI nodes and is ill defined.
Remove it for now and if someone comes up with a good reason and
consistent definition for it we can add it back
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The 'device_type = "soc";' line *is* needed in the DTS for get_immrbase()
to return the correct address.
Signed-off-by: NMartyn Welch <martyn.welch@gefanuc.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Preserve I2C clock settings for the Socrates MPC8544 board.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

For enet2 and enet3 the wrong phy-handles have been used in DTS files
of the TQM8548 modules.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Commit 0f73a449 added I2C device nodes
for the LM75 thermal sensor on the TQM85xx modules, unfortunately with
the wrong I2C address. The LM75s are located at address 0x48.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch adds multi-chip support for the Micron MT29F8G08FAB NAND
flash memory on the TQM8548 modules.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Add aliases, and correct CS0 offset to match how u-boot
programs it (this was not a problem with cuImage because
the wrapper would reprogram the localbus to match the device
tree).
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The device_type "soc" is still required for MPC85xx boards.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

- Add gpio-controller node to manage QE GPIO Bank D;
- Add mmc-spi node;
- Modify board file so that it won't use legacy SPI support with the new
  device trees.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Cc: David Brownell <david-b@pacbell.net>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Kumar Gala <galak@gate.crashing.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Older devices tree's used "fsl,85.." instead of the preferred
"fsl,mpc85.." for the memory controller & l2 cache controller nodes.
The EDAC code is the only use of these and has been updated for some
time to support both "fsl,85.." and "fsl,mpc85.."
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Supported are Ethernet, serial console, I2C, I2C-based RTC and
temperature sensors, NOR and NAND flash, PCI, USB, CAN and Lime
display controller.

The multiplexing of FPGA interrupts onto PowerPC interrupt lines is
supported through our own fpga_pic interrupt controller driver.

For example the SJA1000 controller is level low sensitive connected to
fpga_pic line 2 and is routed to the second (of three) irq lines to
the CPU:

    can@3,100 {
            compatible = "philips,sja1000";
            reg = <3 0x100 0x80>;
            interrupts = <2 2>;
            interrupts = <2 8 1>;   // number, type, routing
            interrupt-parent = <&fpga_pic>;
    };
Signed-off-by: NSergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: NYuri Tikhonov <yur@emcraft.com>
Signed-off-by: NIlya Yanok <yanok@emcraft.com>
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Signed-off-by: NDmitry Rakhchev <rda@emcraft.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The gianfar@25000 node was missing its ranges prop for the mdio bus
and provided an explicit ranges property on gianfar@24000 to match
change from commit:

commit 70b3adbb
Author: Anton Vorontsov <avorontsov@ru.mvista.com>
Date:   Thu Mar 19 21:01:45 2009 +0300

    powerpc/83xx: Move gianfar mdio nodes under the ethernet nodes
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Currently it doesn't matter where the mdio nodes are placed, but with
power management support (i.e. when sleep = <> properties will take
effect), mdio nodes placement will become important: mdio controller
is a part of the ethernet block, so the mdio nodes should be placed
correctly. Otherwise we may wrongly assume that MDIO controllers are
available during sleep.
Suggested-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Currently it doesn't matter where the mdio nodes are placed, but with
power management support (i.e. when sleep = <> properties will take
effect), mdio nodes placement will become important: mdio controller
is a part of the ethernet block, so the mdio nodes should be placed
correctly. Otherwise we may wrongly assume that MDIO controllers are
available during sleep.
Suggested-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Currently it doesn't matter where the mdio nodes are placed, but with
power management support (i.e. when sleep = <> properties will take
effect), mdio nodes placement will become important: mdio controller
is a part of the ethernet block, so the mdio nodes should be placed
correctly. Otherwise we may wrongly assume that MDIO controllers are
available during sleep.
Suggested-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch adds pmc nodes to the device tree files so that the boards
will able to use standby capability of MPC837x processors. The MPC837x
PMC controllers are compatible with MPC8349 ones (i.e. no deep sleep).

sleep = <> properties are used to specify SCCR masks as described
in "Specifying Device Power Management Information (sleep property)"
chapter in Documentation/powerpc/booting-without-of.txt.

Since I2C1 and eSDHC controllers share the same clock source, they
are now placed under sleep-nexus nodes.

A processor is able to wakeup the boards on LAN events (Wake-On-Lan),
console events (with no_console_suspend kernel command line), GPIO
events and external IRQs (IRQ1 and IRQ2).

The processor can also wakeup the boards by the fourth general purpose
timer in GTM1 block, but the GTM wakeup support isn't yet implemented
(it's tested to work, but it's unclear how can we use the quite short
GTM timers, and how do we want to expose the GTM to userspace).
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).

This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: NMartyn Welch <martyn.welch@gefanuc.com>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The PCI irqs for the protected sources where not correct for PCI PHBs
Signed-off-by: NTed Peters <ted.peters@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>