- 02 4月, 2015 1 次提交
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由 Guenter Roeck 提交于
This will let us use the switch product IDs in the common source code. Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 30 3月, 2015 4 次提交
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由 Guenter Roeck 提交于
No vlan support at this time. Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Guenter Roeck 提交于
Bridge support is similar for all chips supported by the mv88e6xxx code, so add the code there. Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Guenter Roeck 提交于
Provide mv88e6xxx_setup_port_common() for common port initialization. Currently only write Port 1 Control and VLAN configuration since this will be needed for hardware bridging. More can be added later if desired/needed. Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Guenter Roeck 提交于
Code used and needed in mv886xxx.c should be initialized there as well, so factor it out from the individual initialization files. Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 08 3月, 2015 1 次提交
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由 Guenter Roeck 提交于
EEE configuration is similar for the various MV88E6xxx chips. Add generic support for it. Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 20 2月, 2015 1 次提交
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由 Andrew Lunn 提交于
The mv88e6352 allows access to the port phys via an internal mdio bus which is accessed using registers in the GLOBAL 2 range. The mv88e6171 and probably other devices use the same mechanism. Move this code into the shared mv88e6xxx.c library. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 17 11月, 2014 1 次提交
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由 Andrew Lunn 提交于
The method to read the temperature used in the mve6123_61_65 driver can also be used for other chips. Move the code into the shared code base of mv88e6xxx.c. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 31 10月, 2014 3 次提交
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由 Guenter Roeck 提交于
The infrastructure can now report switch registers to ethtool. Add support for it to the mv88e6123_61_65 driver. Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Guenter Roeck 提交于
MV88E6352 supports read and write access to its configuration eeprom. There is no means to detect if an EEPROM is connected to the switch. Also, the switch supports EEPROMs with different sizes, but can not detect or report the type or size of connected EEPROMs. Therefore, do not implement the get_eeprom_len callback but depend on platform or devicetree data to provide information about EEPROM presence and size. Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Guenter Roeck 提交于
Marvell 88E6352 is mostly compatible to MV88E6123/61/65, but requires indirect phy access. Also, its configuration registers are a bit different. Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 9月, 2014 1 次提交
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由 Andrew Lunn 提交于
This is the Marvell driver with some cleanups by Claudio Leite and myself. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Cc: Claudio Leite <leitec@staticky.com> Signed-off-by: NClaudio Leite <leitec@staticky.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 1月, 2013 2 次提交
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由 Barry Grussling 提交于
Fix DSA whitespace issues reported by checkpatch.pl Signed-off-by: NBarry Grussling <barry@grussling.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Barry Grussling 提交于
Convert DSA driver comments to network-style comments as reported by checkpatch.pl. Fix spelling error. Signed-off-by: NBarry Grussling <barry@grussling.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 29 11月, 2011 1 次提交
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由 Ben Hutchings 提交于
Support for specific hardware belongs under drivers/net/ not net/. Signed-off-by: NBen Hutchings <ben@decadent.org.uk> Acked-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 27 11月, 2011 1 次提交
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由 Ben Hutchings 提交于
These drivers share a lot of code, so if we make them modular they should be built into the same module. Therefore, link them together and merge their respective module init and exit functions. Signed-off-by: NBen Hutchings <ben@decadent.org.uk> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 07 4月, 2011 1 次提交
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由 Peter Korsgaard 提交于
The mv88e6085 is identical to the mv88e6095, except that all ports are 10/100 Mb/s, so use the existing setup code except for the cpu/dsa speed selection in _setup_port(). Signed-off-by: NPeter Korsgaard <jacmet@sunsite.dk> Acked-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 09 10月, 2008 2 次提交
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由 Lennert Buytenhek 提交于
Add support for the Marvell 88E6131 switch chip. This chip only supports the original (ethertype-less) DSA tagging format. On the 88E6131, there is a PHY Polling Unit (PPU) which has exclusive access to each of the PHYs's MII management registers. If we want to talk to the PHYs from software, we have to disable the PPU and wait for it to complete its current transaction before we can do so, and we need to re-enable the PPU afterwards to make sure that the switch will notice changes in link state and speed on the individual ports as they occur. Since disabling the PPU is rather slow, and since MII management accesses are typically done in bursts, this patch keeps the PPU disabled for 10ms after a software access completes. This makes handling the PPU slightly more complex, but speeds up something like running ethtool on one of the switch slave interfaces from ~300ms to ~30ms on typical hardware. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Tested-by: NNicolas Pitre <nico@marvell.com> Tested-by: NPeter van Valderen <linux@ddcrew.com> Tested-by: NDirk Teurlings <dirk@upexia.nl> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Lennert Buytenhek 提交于
Distributed Switch Architecture is a protocol for managing hardware switch chips. It consists of a set of MII management registers and commands to configure the switch, and an ethernet header format to signal which of the ports of the switch a packet was received from or is intended to be sent to. The switches that this driver supports are typically embedded in access points and routers, and a typical setup with a DSA switch looks something like this: +-----------+ +-----------+ | | RGMII | | | +-------+ +------ 1000baseT MDI ("WAN") | | | 6-port +------ 1000baseT MDI ("LAN1") | CPU | | ethernet +------ 1000baseT MDI ("LAN2") | |MIImgmt| switch +------ 1000baseT MDI ("LAN3") | +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4") | | | | +-----------+ +-----------+ The switch driver presents each port on the switch as a separate network interface to Linux, polls the switch to maintain software link state of those ports, forwards MII management interface accesses to those network interfaces (e.g. as done by ethtool) to the switch, and exposes the switch's hardware statistics counters via the appropriate Linux kernel interfaces. This initial patch supports the MII management interface register layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and supports the "Ethertype DSA" packet tagging format. (There is no officially registered ethertype for the Ethertype DSA packet format, so we just grab a random one. The ethertype to use is programmed into the switch, and the switch driver uses the value of ETH_P_EDSA for this, so this define can be changed at any time in the future if the one we chose is allocated to another protocol or if Ethertype DSA gets its own officially registered ethertype, and everything will continue to work.) Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Tested-by: NNicolas Pitre <nico@marvell.com> Tested-by: NByron Bradley <byron.bbradley@gmail.com> Tested-by: NTim Ellis <tim.ellis@mac.com> Tested-by: NPeter van Valderen <linux@ddcrew.com> Tested-by: NDirk Teurlings <dirk@upexia.nl> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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