Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
1 年多 前同步成功

通知 161
Star 36
Fork 7
cloud-kernel
cloud-kernel
切换分支/标签
  1. 16 11月, 2016 1 次提交
  3. 09 11月, 2016 1 次提交
  5. 29 1月, 2016 1 次提交
  7. 23 10月, 2015 1 次提交
  9. 26 9月, 2015 1 次提交
  11. 17 9月, 2015 1 次提交
  13. 10 9月, 2015 1 次提交
  15. 11 8月, 2015 1 次提交
  17. 16 6月, 2015 1 次提交
    • C
      spi: atmel: add support to FIFOs · 11f2764f
      由 Cyrille Pitchen 提交于 
      The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).

In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).

To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.

When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.

Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.

In pio mode, two data are written in the TDR in a single access.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      11f2764f
  19. 10 6月, 2015 1 次提交
    • C
      spi: atmel: add support for the internal chip-select of the spi controller · 48203034
      由 Cyrille Pitchen 提交于 
      This patch relies on the CSAAT (Chip Select Active After Transfer) feature
introduced by the version 2 of the spi controller. This new mode allows to
use properly the internal chip-select output pin of the spi controller
instead of using external gpios. Consequently, the "cs-gpios" device-tree
property becomes optional.

When the new CSAAT bit is set into the Chip Select Register, the internal
chip-select output pin remains asserted till both the following conditions
become true:
- the LASTXFER bit is set into the Control Register (or the Transmit Data
  Register)
- the Transmit Data Register and its shift register are empty.

WARNING: if the LASTXFER bit is set into the Control Register then new
data are written into the Transmit Data Register fast enough to keep its
shifter not empty, the chip-select output pin remains asserted. Only when
the shifter becomes empty, the chip-select output pin is unasserted.

When the CSAAT bit is clear in the Chip Select Register, the LASTXFER bit
is ignored in both the Control Register and the Transmit Data Register.
The internal chip-select output pin remains active as long as the Transmit
Data Register or its shift register are not empty.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      48203034
  21. 23 3月, 2015 1 次提交
  23. 26 2月, 2015 1 次提交
    • T
      spi: atmel: Fix interrupt setup for PDC transfers · 76e1d14b
      由 Torsten Fleischer 提交于 
      Additionally to the current DMA transfer the PDC allows to set up a next DMA
transfer. This is useful for larger SPI transfers.

The driver currently waits for ENDRX as end of the transfer. But ENDRX is set
when the current DMA transfer is done (RCR = 0), i.e. it doesn't include the
next DMA transfer.
Thus a subsequent SPI transfer could be started although there is currently a
transfer in progress. This can cause invalid accesses to the SPI slave devices
and to SPI transfer errors.

This issue has been observed on a hardware with a M25P128 SPI NOR flash.

So instead of ENDRX we should wait for RXBUFF. This flag is set if there is
no more DMA transfer in progress (RCR = RNCR = 0).
Signed-off-by: NTorsten Fleischer <torfl6749@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
      76e1d14b
  25. 04 2月, 2015 1 次提交
  27. 25 11月, 2014 2 次提交
  29. 22 10月, 2014 1 次提交
  31. 20 10月, 2014 4 次提交
  33. 02 8月, 2014 1 次提交
  35. 17 7月, 2014 1 次提交
  37. 08 5月, 2014 1 次提交
  39. 18 4月, 2014 1 次提交
  41. 15 4月, 2014 1 次提交
  43. 22 3月, 2014 1 次提交
  45. 05 3月, 2014 2 次提交
  47. 03 3月, 2014 2 次提交
  49. 13 2月, 2014 1 次提交
  51. 03 2月, 2014 1 次提交
  53. 10 1月, 2014 1 次提交
  55. 08 1月, 2014 1 次提交
  57. 04 12月, 2013 1 次提交
  59. 23 10月, 2013 1 次提交
  61. 17 10月, 2013 2 次提交
  63. 15 10月, 2013 1 次提交
  65. 07 10月, 2013 1 次提交