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  1. 24 3月, 2013 1 次提交
  3. 15 2月, 2013 1 次提交
  5. 05 12月, 2012 1 次提交
  7. 22 11月, 2012 1 次提交
    • D
      drm/i915: resurrect panel lid handling · a726915c
      由 Daniel Vetter 提交于 
      But disabled by default. This essentially reverts

commit bcd5023c
Author: Dave Airlie <airlied@redhat.com>
Date:   Mon Mar 14 14:17:55 2011 +1000

    drm/i915: disable opregion lid detection for now

but leaves the autodetect mode disabled. There's also the explicit lid
status option added in

commit fca87409
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Thu Feb 17 13:44:48 2011 +0000

    drm/i915: Add a module parameter to ignore lid status

Which overloaded the meaning for the panel_ignore_lid parameter even
more. To fix up this mess, give the non-negative numbers 0,1 the
original meaning back and use negative numbers to force a given state.
So now we have

1  - disable autodetect, return unknown
0  - enable autodetect
-1 - force to disconnected/lid closed
-2 - force to connected/lid open

v2: My C programmer license has been revoked ...

v3: Beautify the code a bit, as suggested by Chris Wilson.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=27622Tested-by: NAndreas Sturmlechner <andreas.sturmlechner@gmail.com>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      a726915c
  9. 12 11月, 2012 1 次提交
  11. 26 10月, 2012 1 次提交
  13. 23 10月, 2012 3 次提交
  15. 04 9月, 2012 1 次提交
  17. 12 8月, 2012 1 次提交
  19. 06 8月, 2012 1 次提交
  21. 20 7月, 2012 1 次提交
    • P
      drm/i915: don't forget the PCH backlight registers · a4f32fc3
      由 Paulo Zanoni 提交于 
      When we enable/disable the CPU backlight registers we can't forget to
enable/disable the PCH backlight registers. Since we're using the CPU
registers we should also unset the override bit.

Fixes a regression on the following commit:
  drm/i915: properly enable the blc controller on the right pipe

The commit just deleted the code that sets the PCH registers, so it
was relying on the values set by the BIOS. I told my BIOS to boot on
the DVI monitor instead of the LVDS panel, so I noticed the bug.
Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      a4f32fc3
  23. 13 6月, 2012 1 次提交
    • D
      drm/i915: properly enable the blc controller on the right pipe · 24ded204
      由 Daniel Vetter 提交于 
      On gen4+ we have a bitfield to specify from which pipe the backlight
controller should take it's clock. For PCH split platforms we've
already set these up, but only at initialization time. And without
taking into account the 3rd pipe added with ivb.

For gen4, we've completely ignored these. Although we do restrict lvds
to the 2nd pipe, so this is only a problem on machines where we boot
up with the lvds on the first pipe.

So restructure the code to enable the backlight on the right pipe at
modeset time.

v2: For odd reasons panel_enable_backlight gets called twice in a
modeset, so we can't WARN_ON in there if the backlight controller is
switched on already.

v3: backlight enable can also be called through dpms on, so the check
in there is legit. Update the comment to reflect that.
Tested-By: NKamal Mostafa <kamal@canonical.com>
Bugzilla: https://bugs.launchpad.net/bugs/954661
Cc: Carsten Emde <C.Emde@osadl.org>
Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      24ded204
  25. 05 6月, 2012 1 次提交
  27. 22 5月, 2012 1 次提交
  29. 16 4月, 2012 1 次提交
  31. 19 3月, 2012 3 次提交
  33. 11 2月, 2012 1 次提交
    • D
      drm/i915: fixup interlaced vertical timings confusion, part 1 · ca9bfa7e
      由 Daniel Vetter 提交于 
      We have a pretty decent confusion about vertical timings of interlaced
modes. Peter Ross has written a patch that makes interlace modes work
on a lot more platforms/output combinations by doubling the vertical
timings.

The issue with that patch is that core drm _does_ support specifying
whether we want these vertical timings in fields or frames, we just
haven't managed to consistently use this facility. The relavant
function is drm_mode_set_crtcinfo, which fills in the crtc timing
information.

The first thing to note is that the drm core keeps interlaced modes in
frames, but displays modelines in fields. So when the crtc modeset
helper copies over the mode into adjusted_mode it will already contain
vertical timings in half-frames. The result is that the fixup code in
intel_crtc_mode_fixup doesn't actually do anything (in most cases at
least).

Now gen3+ natively supports interlaced modes and wants the vertical
timings in frames. Which is what sdvo already fixes up, at least under
some conditions.

There are a few other place that demand vertical timings in fields
but never actually deal with interlaced modes, so use frame timings
for consistency, too. These are:
- lvds panel,
- dvo encoders - dvo is the only way gen2 could support interlaced
  mode, but currently we don't support any encoders that do.
- tv out - despite that the tv dac sends out an interlaced signal it
  expects a progressive mode pipe configuration.
All these encoders enforce progressive modes by resetting
interlace_allowed.

Hence we always want crtc vertical timings in frames. Enforce this in
our crtc mode_fixup function and rip out any redudant timing
computations from the encoders' mode_fixup function.

v2-4: Adjust the vertical timings a bit.

v5: Split out the 'subtract-one for interlaced' fixes.

v6: Clarify issues around tv-out and gen2.
Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: NChristopher Egert <cme3000@gmail.com>
Tested-by: NAlfonso Fiore <alfonso.fiore@gmail.com>
Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ca9bfa7e
  35. 17 1月, 2012 1 次提交
  37. 24 11月, 2011 1 次提交
    • K
      drm/i915: Treat pre-gen4 backlight duty cycle value consistently · ca88479c
      由 Keith Packard 提交于 
      For i945 and earlier chips, the backlight frequency value had the low
bit (of 16) fixed to zero. The Pineview code path handled this by just
exposing the backlight range as 15 bits while other chips had the
backlight range limited to 0 .. 0xfffe.

This patch makes everyone take the pineview code path, providing 15
bits of backlight duty cycle range which seems more than sufficient to
me.

Daniel Mack reported that writing 1 to bit 0 of the duty cycle
register was causing problems on his Samsung X20 notebook, even when
the duty cycle value was less than the maximum backlight value. (He
tried a value of 29749 with max_brightness of 29750). This patch never
writes a '1' to that bit.
Signed-off-by: NKeith Packard <keithp@keithp.com>
Reviewed-by: NTakashi Iwai <tiwai@suse.de>
Reported-and-tested-by: NDaniel Mack <zonque@gmail.com>
Cc: stable@kernel.org
      ca88479c
  39. 18 11月, 2011 1 次提交
  41. 21 10月, 2011 1 次提交
    • T
      drm/i915/panel: Always record the backlight level again (but cleverly) · f52c619a
      由 Takashi Iwai 提交于 
      The commit 47356eb6 introduced a
mechanism to record the backlight level only at disabling time, but it
also introduced a regression.  Since intel_lvds_enable() may be called
without disabling (e.g. intel_lvds_commit() calls it unconditionally),
the backlight gets back to the last recorded value.  For example, this
happens when you dim the backlight, close the lid and open the lid,
then the backlight suddenly goes to the brightest.

This patch fixes the bug by recording the backlight level always
when changed via intel_panel_set_backlight().  And,
intel_panel_{enable|disable}_backlight() call the internal function not
to update the recorded level wrongly.

Cc: <stable@kernel.org>
Signed-off-by: NTakashi Iwai <tiwai@suse.de>
Reviewed-by: NKeith Packard <keithp@keithp.com>
Signed-off-by: NKeith Packard <keithp@keithp.com>
      f52c619a
  43. 20 9月, 2011 1 次提交
  45. 16 8月, 2011 1 次提交
  47. 26 7月, 2011 1 次提交
    • A
      drm/i915/pch: Fix integer math bugs in panel fitting · 302983e9
      由 Adam Jackson 提交于 
      Consider a 1600x900 panel, upscaling a 1360x768 mode, full-aspect.  The
old math would give you:

    scaled_width  = 1600 * 768;         /* 1228800 */
    scaled_height = 1360 * 900;         /* 1224000 */
    if (scaled_width > scaled_height) { /* pillarbox, and true */
        width  = 1224000 / 768;         /* int(1593.75) = 1593 */
        x      = (1600 - 1593 + 1) / 2; /* 4 */
        y      = 0;
        height = 768;
    } /* ... */

This is broken.  The total width of scanout would then be 1593 + 4 + 4,
or 1601, which is wider than the panel itself.  The hardware very
dutifully implements this, and you end up with a black 45° diagonal from
the top-left corner to the bottom edge of the screen.  It's a cool
effect and all, but not what you wanted.  Similar things happen for the
letterbox case.

The problem is that you have an integer number of pixels, which means
it's usually impossible to upscale equally on both axes.  1360/768 is
1.7708, 1600/900 is 1.7777.  Since we're constrained on the one axis,
the other one wants to come out as an even number of pixels (the panel
is almost certainly even on both axes, and the x/y offsets will be
applied on both sides).  In the math above, if 'width' comes out even,
rounding down is correct; if it's odd, you'd rather round up.  So just
increment width/height in those cases.

Tested on a Lenovo T500 (Ironlake).
Signed-off-by: NAdam Jackson <ajax@redhat.com>
Tested-By: NDaniel Manrique <daniel.manrique@canonical.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38851Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
Signed-off-by: NKeith Packard <keithp@keithp.com>
      302983e9
  49. 14 3月, 2011 1 次提交
  51. 11 3月, 2011 1 次提交
  53. 22 2月, 2011 2 次提交
    • C
      drm/i915: Add a module parameter to ignore lid status · fca87409
      由 Chris Wilson 提交于 
      Seems like we are forever to be cursed with buggy firmware, so allow the
user to explicitly set the panel connection status.

Of secondary utility for cases where I run laptops with the lid closed,
but still want to configure the LVDS.
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      fca87409
    • I
      drm/i915: Do not handle backlight combination mode specially · 951f3512
      由 Indan Zupancic 提交于 
      The current code does not follow Intel documentation: It misses some things
and does other, undocumented things. This causes wrong backlight values in
certain conditions. Instead of adding tricky code handling badly documented
and rare corner cases, don't handle combination mode specially at all. This
way PCI_LBPC is never touched and weird things shouldn't happen.

If combination mode is enabled, then the only downside is that changing the
brightness has a greater granularity (the LBPC value), but LBPC is at most
254 and the maximum is in the thousands, so this is no real functional loss.

A potential problem with not handling combined mode is that a brightness of
max * PCI_LBPC is not bright enough. However, this is very unlikely because
from the documentation LBPC seems to act as a scaling factor and doesn't look
like it's supposed to be changed after boot. The value at boot should always
result in a bright enough screen.

IMPORTANT: However, although usually the above is true, it may not be when
people ran an older (2.6.37) kernel which messed up the LBPC register, and
they are unlucky enough to have a BIOS that saves and restores the LBPC value.
Then a good kernel may seem to not work: Max brightness isn't bright enough.
If this happens people should boot back into the old kernel, set brightness
to the maximum, and then reboot. After that everything should be fine.

For more information see the below links. This fixes bugs:

  http://bugzilla.kernel.org/show_bug.cgi?id=23472
  http://bugzilla.kernel.org/show_bug.cgi?id=25072Signed-off-by: NIndan Zupancic <indan@nul.nu>
Tested-by: NAlex Riesen <raa.lkml@gmail.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      951f3512
  55. 16 2月, 2011 1 次提交
  57. 13 1月, 2011 1 次提交
  59. 12 1月, 2011 1 次提交
  61. 23 11月, 2010 1 次提交
  63. 21 9月, 2010 1 次提交
  65. 08 9月, 2010 1 次提交
  67. 10 8月, 2010 1 次提交