1. 04 7月, 2013 1 次提交
    • J
      mm/tile: use common help functions to free reserved pages · abd1b6d6
      Jiang Liu 提交于
      Use common help functions to free reserved pages.
      Signed-off-by: NJiang Liu <jiang.liu@huawei.com>
      Cc: Chris Metcalf <cmetcalf@tilera.com>
      Cc: Wen Congyang <wency@cn.fujitsu.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: "Michael S. Tsirkin" <mst@redhat.com>
      Cc: <sworddragon2@aol.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Jeremy Fitzhardinge <jeremy@goop.org>
      Cc: Jianguo Wu <wujianguo@huawei.com>
      Cc: Joonsoo Kim <js1304@gmail.com>
      Cc: Kamezawa Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
      Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Cc: Marek Szyprowski <m.szyprowski@samsung.com>
      Cc: Mel Gorman <mel@csn.ul.ie>
      Cc: Michel Lespinasse <walken@google.com>
      Cc: Minchan Kim <minchan@kernel.org>
      Cc: Rik van Riel <riel@redhat.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Tang Chen <tangchen@cn.fujitsu.com>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      abd1b6d6
  2. 24 2月, 2013 1 次提交
  3. 19 7月, 2012 2 次提交
    • C
      arch/tile: enable ZONE_DMA for tilegx · eef015c8
      Chris Metcalf 提交于
      This is required for PCI root complex legacy support and USB OHCI root
      complex support.  With this change tilegx now supports allocating memory
      whose PA fits in 32 bits.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      eef015c8
    • C
      tilegx pci: support I/O to arbitrarily-cached pages · bbaa22c3
      Chris Metcalf 提交于
      The tilegx PCI root complex support (currently only in linux-next)
      is limited to pages that are homed on cached in the default manner,
      i.e. "hash-for-home".  This change supports delivery of I/O data to
      pages that are cached in other ways (locally on a particular core,
      uncached, user-managed incoherent, etc.).
      
      A large part of the change is supporting flushing pages from cache
      on particular homes so that we can transition the data that we are
      delivering to or from the device appropriately.  The new homecache_finv*
      routines handle this.
      
      Some changes to page_table_range_init() were also required to make
      the fixmap code work correctly on tilegx; it hadn't been used there
      before.
      
      We also remove some stub mark_caches_evicted_*() routines that
      were just no-ops anyway.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      bbaa22c3
  4. 26 5月, 2012 3 次提交
    • C
      arch/tile: support multiple huge page sizes dynamically · 621b1955
      Chris Metcalf 提交于
      This change adds support for a new "super" bit in the PTE, using the new
      arch_make_huge_pte() method.  The Tilera hypervisor sees the bit set at a
      given level of the page table and gangs together 4, 16, or 64 consecutive
      pages from that level of the hierarchy to create a larger TLB entry.
      
      One extra "super" page size can be specified at each of the three levels
      of the page table hierarchy on tilegx, using the "hugepagesz" argument
      on the boot command line.  A new hypervisor API is added to allow Linux
      to tell the hypervisor how many PTEs to gang together at each level of
      the page table.
      
      To allow pre-allocating huge pages larger than the buddy allocator can
      handle, this change modifies the Tilera bootmem support to put all of
      memory on tilegx platforms into bootmem.
      
      As part of this change I eliminate the vestigial CONFIG_HIGHPTE support,
      which never worked anyway, and eliminate the hv_page_size() API in favor
      of the standard vma_kernel_pagesize() API.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      621b1955
    • C
      arch/tile: Allow tilegx to build with either 16K or 64K page size · d5d14ed6
      Chris Metcalf 提交于
      This change introduces new flags for the hv_install_context()
      API that passes a page table pointer to the hypervisor.  Clients
      can explicitly request 4K, 16K, or 64K small pages when they
      install a new context.  In practice, the page size is fixed at
      kernel compile time and the same size is always requested every
      time a new page table is installed.
      
      The <hv/hypervisor.h> header changes so that it provides more abstract
      macros for managing "page" things like PFNs and page tables.  For
      example there is now a HV_DEFAULT_PAGE_SIZE_SMALL instead of the old
      HV_PAGE_SIZE_SMALL.  The various PFN routines have been eliminated and
      only PA- or PTFN-based ones remain (since PTFNs are always expressed
      in fixed 2KB "page" size).  The page-table management macros are
      renamed with a leading underscore and take page-size arguments with
      the presumption that clients will use those macros in some single
      place to provide the "real" macros they will use themselves.
      
      I happened to notice the old hv_set_caching() API was totally broken
      (it assumed 4KB pages) so I changed it so it would nominally work
      correctly with other page sizes.
      
      Tag modules with the page size so you can't load a module built with
      a conflicting page size.  (And add a test for SMP while we're at it.)
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      d5d14ed6
    • C
      arch/tile: use interrupt critical sections less · 51007004
      Chris Metcalf 提交于
      In general we want to avoid ever touching memory while within an
      interrupt critical section, since the page fault path goes through
      a different path from the hypervisor when in an interrupt critical
      section, and we carefully decided with tilegx that we didn't need
      to support this path in the kernel.  (On tilepro we did implement
      that path as part of supporting atomic instructions in software.)
      
      In practice we always need to touch the kernel stack, since that's
      where we store the interrupt state before releasing the critical
      section, but this change cleans up a few things.  The IRQ_ENABLE
      macro is split up so that when we want to enable interrupts in a
      deferred way (e.g. for cpu_idle or for interrupt return) we can
      read the per-cpu enable mask before entering the critical section.
      The cache-migration code is changed to use interrupt masking instead
      of interrupt critical sections.  And, the interrupt-entry code is
      changed so that we defer loading "tp" from per-cpu data until after
      we have released the interrupt critical section.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      51007004
  5. 03 4月, 2012 2 次提交
  6. 29 3月, 2012 1 次提交
  7. 03 8月, 2011 1 次提交
  8. 25 5月, 2011 1 次提交
  9. 11 3月, 2011 1 次提交
    • C
      arch/tile: support 4KB page size as well as 64KB · 76c567fb
      Chris Metcalf 提交于
      The Tilera architecture traditionally supports 64KB page sizes
      to improve TLB utilization and improve performance when the
      hardware is being used primarily to run a single application.
      
      For more generic server scenarios, it can be beneficial to run
      with 4KB page sizes, so this commit allows that to be specified
      (by modifying the arch/tile/include/hv/pagesize.h header).
      
      As part of this change, we also re-worked the PTE management
      slightly so that PTE writes all go through a __set_pte() function
      where we can do some additional validation.  The set_pte_order()
      function was eliminated since the "order" argument wasn't being used.
      
      One bug uncovered was in the PCI DMA code, which wasn't properly
      flushing the specified range.  This was benign with 64KB pages,
      but with 4KB pages we were getting some larger flushes wrong.
      
      The per-cpu memory reservation code also needed updating to
      conform with the newer percpu stuff; before it always chose 64KB,
      and that was always correct, but with 4KB granularity we now have
      to pay closer attention and reserve the amount of memory that will
      be requested when the percpu code starts allocating.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      76c567fb
  10. 02 3月, 2011 4 次提交
  11. 25 11月, 2010 1 次提交
    • C
      drivers/net/tile/: on-chip network drivers for the tile architecture · e5a06939
      Chris Metcalf 提交于
      This change adds the first network driver for the tile architecture,
      supporting the on-chip XGBE and GBE shims.
      
      The infrastructure is present for the TILE-Gx networking drivers (another
      three source files in the new directory) but for now the the actual
      tilegx sources are waiting on releasing hardware to initial customers.
      
      Note that arch/tile/include/hv/* are "upstream" headers from the
      Tilera hypervisor and will probably benefit less from LKML review.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      e5a06939
  12. 02 11月, 2010 1 次提交
  13. 16 10月, 2010 1 次提交
  14. 07 7月, 2010 1 次提交
    • C
      arch/tile: Miscellaneous cleanup changes. · 0707ad30
      Chris Metcalf 提交于
      This commit is primarily changes caused by reviewing "sparse"
      and "checkpatch" output on our sources, so is somewhat noisy, since
      things like "printk() -> pr_err()" (or whatever) throughout the
      codebase tend to get tedious to read.  Rather than trying to tease
      apart precisely which things changed due to which type of code
      review, this commit includes various cleanups in the code:
      
      - sparse: Add declarations in headers for globals.
      - sparse: Fix __user annotations.
      - sparse: Using gfp_t consistently instead of int.
      - sparse: removing functions not actually used.
      - checkpatch: Clean up printk() warnings by using pr_info(), etc.;
        also avoid partial-line printks except in bootup code.
        - checkpatch: Use exposed structs rather than typedefs.
        - checkpatch: Change some C99 comments to C89 comments.
      
      In addition, a couple of minor other changes are rolled in
      to this commit:
      
      - Add support for a "raise" instruction to cause SIGFPE, etc., to be raised.
      - Remove some compat code that is unnecessary when we fully eliminate
        some of the deprecated syscalls from the generic syscall ABI.
      - Update the tile_defconfig to reflect current config contents.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      0707ad30
  15. 05 6月, 2010 1 次提交