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  1. 13 10月, 2007 6 次提交
  3. 21 9月, 2007 1 次提交
  5. 20 7月, 2007 11 次提交
  7. 10 7月, 2007 6 次提交
  9. 21 6月, 2007 1 次提交
    • T
      ahci: fix PORTS_IMPL override · a3d2cc5e
      由 Tejun Heo 提交于 
      If PORTS_IMPL register is zero, ahci initialize it to full mask
corresponding to nr_ports in the CAP register.  hpriv->cap, which is
initialized at the end of the function, is incorrectly used as value
of CAP causing ahci to always override PORTS_IMPL to 0x1 if it's zero.
Fix it.

This fixes a bug where early ich6 ahci can only access the first port.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      a3d2cc5e
  11. 10 6月, 2007 1 次提交
  13. 22 5月, 2007 2 次提交
  15. 16 5月, 2007 1 次提交
    • T
      libata-acpi: add ATA_FLAG_ACPI_SATA port flag · 3cadbcc0
      由 Tejun Heo 提交于 
      Whether a controller needs IDE or SATA ACPI hierarchy is determined by
the programming interface of the controller not by whether the
controller is SATA or PATA, or it supports slave device or not.  This
patch adds ATA_FLAG_ACPI_SATA port flags which tells libata-acpi that
the port needs SATA ACPI nodes, and sets the flag for ahci and
sata_sil24.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      3cadbcc0
  17. 12 5月, 2007 2 次提交
  19. 01 5月, 2007 2 次提交
    • T
      libata: improve 0xff status handling · 9b89391c
      由 Tejun Heo 提交于 
      For PATA, 0xff status indicates empty port.  For SATA, it depends on
how the controller emulates status register.  On some controllers,
0xff is used to represent broken link or certain stage during reset.

libata currently deals SATA the same.  This hasn't caused any problem
because problematic situations usually only occur after hotplug or
other link disruption events and libata blindly waited for the device
to spin up and settle after hotplug giving the link and device
whatever time to go through those stages.

libata is going to replace unconditional spinup wait with generic
timed sequence of resets, so not only getting 0xff handling right for
SATA is, well, the right thing to do, it's much more important now.

This patch makes the following changes.

* Make ata_bus_softreset() return -ENODEV if any of its wait fails
  due to 0xff status.

* Fail soft/hardreset if status wait returns -ENODEV indicating 0xff
  status while SStatus says the link is online.  e.g. Reset fails if
  status is 0xff after reset when SStatus reports the linke is online.
  If SCR registers are not available, everything is the same as
  before.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      9b89391c
    • T
      libata: add deadline support to prereset and reset methods · d4b2bab4
      由 Tejun Heo 提交于 
      Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function.  This patch is in preparation for EH timing
improvements.

* ata_wait_ready() never does busy sleep.  It's only used from EH and
  no wait in EH is that urgent.  This function also prints 'be
  patient' message automatically after 5 secs of waiting if more than
  3 secs is remaining till deadline.

* ata_bus_post_reset() now fails with error code if any of its wait
  fails.  This is important because earlier reset tries will have
  shorter timeout than the spec requires.  If a device fails to
  respond before the short timeout, reset should be retried with
  longer timeout rather than silently ignoring the device.

  There are three behavior differences.

  1. Timeout is applied to both devices at once, not separately.  This
     is more consistent with what the spec says.

  2. When a device passes devchk but fails to become ready before
     deadline.  Previouly, post_reset would just succeed and let
     device classification remove the device.  New code fails the
     reset thus causing reset retry.  After a few times, EH will give
     up disabling the port.

  3. When slave device passes devchk but fails to become accessible
     (TF-wise) after reset.  Original code disables dev1 after 30s
     timeout and continues as if the device doesn't exist, while the
     patched code fails reset.  When this happens, new code fails
     reset on whole port rather than proceeding with only the primary
     device.

  If the failing device is suffering transient problems, new code
  retries reset which is a better behavior.  If the failing device is
  actually broken, the net effect is identical to it, but not to the
  other device sharing the channel.  In the previous code, reset would
  have succeeded after 30s thus detecting the working one.  In the new
  code, reset fails and whole port gets disabled.  IMO, it's a
  pathological case anyway (broken device sharing bus with working
  one) and doesn't really matter.

* ata_bus_softreset() is changed to return error code from
  ata_bus_post_reset().  It used to return 0 unconditionally.

* Spin up waiting is to be removed and not converted to honor
  deadline.

* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      d4b2bab4
  21. 29 4月, 2007 7 次提交
    • T
      ahci: consolidate common port flags · 1188c0d8
      由 Tejun Heo 提交于 
      Consolidate common port flags into AHCI_FLAG_COMMON.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      1188c0d8
    • T
      libata: convert the remaining SATA drivers to new init model · 4447d351
      由 Tejun Heo 提交于 
      Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.

Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths.  This simplifies code quite a bit.

* init_one()'s now follow more consistent init order

* ahci_setup_port() and ahci_host_init() collapsed into
  ahci_init_one() for init order consistency

* sata_vsc uses port_info instead of setting fields manually

* in sata_svw, k2_board_info converted to port_info (info is now in
  port flags).  port number is honored now.

Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      4447d351
    • T
      ahci: add PCI ID for new VIA chip · bf335542
      由 Tejun Heo 提交于 
      Add PCI ID for new VIA chip.  Original patch is from Maarten Vanraes.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Maarten Vanraes <maarten.vanraes@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      bf335542
    • C
      ahci.c: remove non-existing SB600 raid id (re-send) · c65ec1c2
      由 Conke Hu 提交于 
          SB600 RAID and SB600 SATA is the same controller and share the
same PCI ID 0x4380. There is no such PCI ID 0x4381.
Signed-off-by: NConke Hu <conke.hu@gmail.com>
 ---------
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      c65ec1c2
    • T
      libata: improve AC_ERR_DEV handling for ->post_internal_cmd · a51d644a
      由 Tejun Heo 提交于 
      ->post_internal_cmd is simplified EH for internal commands.  Its
primary mission is to stop the controller such that no rogue memory
access or other activities occur after the internal command is
released.  It may provide error diagnostics by setting qc->err_mask
but this hasn't been a requirement.

To ignore SETXFER failure for CFA devices, libata needs to know
whether a command was failed by the device or for any other reason.
ie. internal command needs to get AC_ERR_DEV right.

This patch makes the following changes to AC_ERR_DEV handling and
->post_internal_cmd semantics to accomodate this need and simplify
callback implementation.

1. As long as the correct bits in the result TF registers are set,
   there is no need to set AC_ERR_DEV explicitly.  libata EH core
   takes care of that for both normal and internal commands.

2. The only requirement for ->post_internal_cmd() is to put the
   controller into quiescent state.  It needs not to set any err_mask.

3. ata_exec_internal_sg() performs minimal error analysis such that
   AC_ERR_DEV is automatically set as long as result_tf is filled
   correctly.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      a51d644a
    • T
      ahci: move port_map handling to ahci_save_initial_config() · 17199b18
      由 Tejun Heo 提交于 
      Move cross checking between port_map and cap.n_ports into
ahci_save_initial_config().  After save_initial_config is done,
hpriv->port_map is always setup properly.

Tested on JMB363, ICH7 and ICH8 (with dummy ports).
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      17199b18
    • T
      ahci: implement ata_save/restore_initial_config() · d447df14
      由 Tejun Heo 提交于 
      There are several registers which describe how the controller is
configured.  These registers are sometimes implemented as r/w
registers which are configured by firmware and get cleared on
controller reset or after suspend/resume cycle.  ahci saved and
restored those values inside ahci_reset_controller() which is a bit
messy and doesn't work over suspend/resume cycle.

This patch implements ahci_save/restore_initial_config().  The save
function is called during driver initialization and saves cap and
port_map to hpriv.  The restore function is called after the
controller is reset to restore the initial values.

Sometimes the initial firmware values are inconsistent and need to be
fixed up.  This is handled by ahci_save_initial_config().  For this,
there are two versions of saved registers.  One to write back to the
hardware register, the other to use during driver operation.  This is
necessary to keep ahci's behavior unchanged (write back fixed up
port_map while keeping cap as-is).

This patch makes ahci save the register values once before the first
controller reset, not after it's been reset.  Also, the same stored
values are used written back after each reset, so the register values
are properly recovered after suspend/resume cycle.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      d447df14