- 03 6月, 2015 2 次提交
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由 Yair Shachar 提交于
This patch adds new interface functions to the kfd2kgd interface file. The new functions allow to perform H/W debugger operations by writing to GPU registers. Signed-off-by: NYair Shachar <yair.shachar@amd.com> Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
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由 Joe Perches 提交于
Use the generic mechanism to declare a bitmap instead of unsigned long. It seems that "struct kfd_process.allocated_queue_bitmap" is unused. Maybe it could be deleted instead. Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
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- 02 6月, 2015 2 次提交
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由 Dave Airlie 提交于
Merge tag 'drm-intel-next-fixes-2015-05-29' of git://anongit.freedesktop.org/drm-intel into drm-next Fixes for 4.2. Nothing too serious (given that it's still pre merge window). With that it's off for 2 weeks of vacation for me and taking care of 4.2 fixes for Jani. * tag 'drm-intel-next-fixes-2015-05-29' of git://anongit.freedesktop.org/drm-intel: drm/i915: limit PPGTT size to 2GB in 32-bit platforms drm/i915: Another fbdev hack to avoid PSR on fbcon. drm/i915: Return the frontbuffer flip to enable intel_crtc_enable_planes. drm/i915: disable IPS while getting the sink CRCs drm/i915: Disable 12bpc hdmi for now drm/i915: Adjust sideband locking a bit for CHV/VLV drm/i915: s/dpio_lock/sb_lock/ drm/i915: Kill intel_flush_primary_plane() drm/i915: Throw out WIP CHV power well definitions drm/i915: Use the default 600ns LDO programming sequence delay drm/i915: Remove unnecessary null check in execlists_context_unqueue drm/i915: Use spinlocks for checking when to waitboost drm/i915: Fix the confusing comment about the ioctl limits Revert "drm/i915: Force clean compilation with -Werror"
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由 Alexandre Courbot 提交于
dma_alloc_coherent() can return memory in the vmalloc range. virt_to_page() cannot handle such addresses and crashes. This patch detects such cases and obtains the struct page * using vmalloc_to_page() instead. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Acked-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 30 5月, 2015 1 次提交
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由 Michel Thierry 提交于
We already set this limit for the GGTT. This is a temporary patch until a full replacement of size_t variables (inadequate in 32-bit kernel) is in place. Regression from: commit a4e0bedc Author: Michel Thierry <michel.thierry@intel.com> Date: Wed Apr 8 12:13:35 2015 +0100 drm/i915: Use complete address space in true PPGTT v2: Prettify code and explain why this is needed. (Chris) v3: Don't hide the compilation warning in 32-bit. (Chris) Suggested-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NMichel Thierry <michel.thierry@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 29 5月, 2015 7 次提交
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由 Rodrigo Vivi 提交于
With unified modeset and flip paths introduced recently when switching to fbcon PSR was being disabled on fb_set_par path but re-enabled on fb_pan_display one, causing missed screen updates and un unusable console. Regression introduced with: commit bb546623 Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Tue Apr 21 17:13:13 2015 +0300 drm/i915: Unify modeset and flip paths of intel_crtc_set_config() Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Rodrigo Vivi 提交于
Without this frontbuffer flip when enabling planes PSR got compromised and wasn't being enabled waiting forever on the flush that never arrived. Another solution would to create a enable_cursor function and split this frontbuffer flip among the different plane enable and disable functions. But if necessary this can be done in a follow up work. For now let's just fix the regression. It was removed by: commit 87d4300a Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Date: Tue Apr 21 17:12:54 2015 +0300 drm/i915: Move intel_(pre_disable/post_enable)_primary to intel_display.c, and use it there. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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git://ftp.arm.linux.org.uk/~rmk/linux-arm由 Dave Airlie 提交于
warning fix for tda998x * 'drm-tda998x-devel' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: drm/i2c: tda998x: fix compiler warning for ssize_t
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由 Russell King 提交于
The drm_mm debugfs output is difficult to read as two different formats are used for the addresses: 0x00000080000000-0x0000008000b000: 45056: used 0x8000b000-0x80016000: 45056: free 0x00000080016000-0x0000008001b000: 20480: used 0x8001b000-0x817a1000: 24666112: free 0x000000817a1000-0x000000817a8000: 28672: used 0x000000817a8000-0x00000081ba8000: 4194304: used Fix this by using %#018llx for all addresses, thus making the output: 0x0000000080000000-0x000000008000b000: 45056: used 0x000000008000b000-0x0000000080016000: 45056: free 0x0000000080016000-0x000000008001b000: 20480: used 0x000000008001b000-0x00000000817a1000: 24666112: free 0x00000000817a1000-0x00000000817a8000: 28672: used 0x00000000817a8000-0x0000000081ba8000: 4194304: used Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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git://anongit.freedesktop.org/drm-intel由 Dave Airlie 提交于
- cpt modeset sequence fixes from Ville - more rps boosting tuning from Chris - S3 support for skl (Damien) - a pile of w/a for bxt from various people - cleanup of primary plane pixel formats (Damien) - a big pile of small patches with fixes and cleanups all over * tag 'drm-intel-next-2015-05-22' of git://anongit.freedesktop.org/drm-intel: (90 commits) drm/i915: Update DRIVER_DATE to 20150522 drm/i915: Introduce DRM_I915_THROTTLE_JIFFIES drm/i915: Use the correct destructor for freeing requests on error drm/i915/skl: don't fail colorkey + scaler request drm/i915: Enable GTT caching on gen8 drm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_gating() drm/i915: Use ilk_init_lp_watermarks() on BDW drm/i915: Disable FDI RX/TX before the ports drm/i915: Disable CRT port after pipe on PCH platforms drm/i915: Disable SDVO port after the pipe on PCH platforms drm/i915: Disable HDMI port after the pipe on PCH platforms drm/i915: Fix the IBX transcoder B workarounds drm/i915: Write the SDVO reg twice on IBX drm/i915: Fix DP enhanced framing for CPT drm/i915: Clean up the CPT DP .get_hw_state() port readout drm/i915: Clarfify the DP code platform checks drm/i915: Remove the double register write from intel_disable_hdmi() drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi() drm/i915/skl: Deinit/init the display at suspend/resume drm/i915: Free RPS boosts for all laggards ...
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git://people.freedesktop.org/~agd5f/linux由 Dave Airlie 提交于
for amdgpu separately next week. Highlights for radeon: - VCE1 support - Bug fixes and misc cleanups * 'drm-next-4.2' of git://people.freedesktop.org/~agd5f/linux: radeon: Deinline indirect register accessor functions drm/radeon: Fix max_vblank_count value for current display engines drm/radeon: stop using addr to check for BO move drm/radeon: clean up radeon_audio_enable drm/radeon: take the mode_config mutex when dealing with hpds (v2) drm/radeon: make dpcd parameters const drm/radeon: Use DECLARE_BITMAP drm/radeon/tn/si: enable/disable vce cg when encoding v2 drm/radeon: add support for vce 1.0 clock gating drm/radeon: add VCE 1.0 support v4 drm/radeon/dpm: add vce support for SI drm/radeon/dpm: add vce dpm support for TN drm/radeon: implement tn_set_vce_clocks drm/radeon: implement si_set_vce_clocks v2 drm/radeon: allow some more VCE firmware versions drm/radeon: rework VCE FW size calculation drm/radeon: add a GPU reset counter queryable by userspace
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由 Denys Vlasenko 提交于
This patch deinlines indirect register accessor functions. These functions perform two mmio accesses, framed by spin lock/unlock. Spin lock/unlock by itself takes more than 50 cycles in ideal case (if lock is exclusively cached on current CPU). With this .config: http://busybox.net/~vda/kernel_config, after uninlining these functions have sizes and callsite counts as follows: r600_uvd_ctx_rreg: 111 bytes, 4 callsites r600_uvd_ctx_wreg: 113 bytes, 5 callsites eg_pif_phy0_rreg: 106 bytes, 13 callsites eg_pif_phy0_wreg: 108 bytes, 13 callsites eg_pif_phy1_rreg: 107 bytes, 13 callsites eg_pif_phy1_wreg: 108 bytes, 13 callsites rv370_pcie_rreg: 111 bytes, 21 callsites rv370_pcie_wreg: 113 bytes, 24 callsites r600_rcu_rreg: 111 bytes, 16 callsites r600_rcu_wreg: 113 bytes, 25 callsites cik_didt_rreg: 106 bytes, 10 callsites cik_didt_wreg: 107 bytes, 10 callsites tn_smc_rreg: 106 bytes, 126 callsites tn_smc_wreg: 107 bytes, 116 callsites eg_cg_rreg: 107 bytes, 20 callsites eg_cg_wreg: 108 bytes, 52 callsites Functions r100_mm_rreg() and r100_mm_rreg() have a fast path and a locked (slow) path. This patch deinlines only slow path. r100_mm_rreg_slow: 78 bytes, 2083 callsites r100_mm_wreg_slow: 81 bytes, 3570 callsites Reduction in code size is more than 65,000 bytes: text data bss dec hex filename 85740176 22294680 20627456 128662312 7ab3b28 vmlinux.before 85674192 22294776 20627456 128598664 7aa4288 vmlinux Signed-off-by: NDenys Vlasenko <dvlasenk@redhat.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: linux-kernel@vger.kernel.org Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 28 5月, 2015 10 次提交
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由 Paulo Zanoni 提交于
This commit is the "sink CRC" version of: commit 8c740dce Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Fri Oct 17 18:42:03 2014 -0300 drm/i915: disable IPS while getting the pipe CRCs. For some unknown reason, when IPS gets enabled, the sink CRC changes. Since hsw_enable_ips() doesn't really guarantee to enable IPS (it depends on package C-states), we can't really predict if IPS is enabled or disabled while running our CRC tests, so let's just completely disable IPS while sink CRCs are being used. If we find a way to make IPS not change the pipe CRC result, we may want to fix IPS and then revert this patch (and 8c740dce too). While this doesn't happen, let's merge this patch, so the IGT tests relying on sink CRCs can work properly. This was discovered while developing a new IGT test, which will probably be called kms_frontbuffer_tracking. Testcase: igt/kms_frontbuffer_tracking (not on upstream IGT yet) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
It's totally broken, and since commit d328c9d7 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Fri Apr 10 16:22:37 2015 +0200 drm/i915: Select starting pipe bpp irrespective or the primary plane the kernel will try to use it even for the common rgb888 framebuffers. Ville has patches to fix it all up properly, but unfortunately they're stuck in review limbo. And since the 4.2 feature cutoff has passed we need to somehow handle this regression. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Paulo Zanoni <przanoni@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
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由 Ville Syrjälä 提交于
chv_enable_pll() doesn't need to hold sb_lock for the entire duration of the function. Drop the lock as soon as possible. valleyview_set_cdclk() does a potential lock+unlock+lock+unlock cycle with sb_lock. Grab the lock a few lines earlier so we can make do with a single lock+unlock cycle always. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NJani Nikula <jani.nikula@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Rename dpio_lock to sb_lock to inform the reader that its primary purpose is to protect the sideband mailbox rather than some DPIO state. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NJani Nikula <jani.nikula@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
The primary plane frobbing was removed from the sprite code in commit ecce87ea Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Date: Tue Apr 21 17:12:50 2015 +0300 drm/i915: Remove implicitly disabling primary plane for now but the intel_flush_primary_plane() calls were left behind. Replace them with straight forward POSTING_READ() of the sprite surface address register. The other user of intel_flush_primary_plane() is g4x_disable_trickle_feed() where we can just inline the steps directly. This allows intel_flush_primary_plane() to be killed off. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Expecting CHV power wells to be just an extended versions of the VLV power wells, a bunch of commented out power wells were added in anticipation when Punit folks would implement it all. Turns out they never did, and instead CHV has fewer power wells than VLV. Rip out all the #if 0'ed junk that's not needed. v2: Rename the "pipe-a" well to "display" to match VLV Clarify the pipe A power well relationship to pipes B and C (Deepak) Reviewed-by: NDeepak S <deepak.s@linux.intel.com> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Not sure which LDO programming sequence delay should be used for the CHV PHY, but the spec says that 600ns is "Used by default for initial bringup", and the BIOS seems to use that, so let's do the same. Reviewed-by: NDeepak S <deepak.s@linux.intel.com> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Michel Dänzer 提交于
The value was much too low, which could cause the userspace visible vblank counter to move backwards when the hardware counter wrapped around. Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
It is theoretically possible that a swapped out BO gets the same GTT address, but different backing pages while being swapped in. Instead just use another VA state to note updated areas. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
- make it static - fix mask/bool handling for last param Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 27 5月, 2015 2 次提交
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由 Michel Thierry 提交于
commit 53292cdb ("drm/i915: Workaround to avoid lite restore with HEAD==TAIL") added a check for req0 != null which is unnecessary. The only way req0 could be null is if the list was empty, and this is already addressed at the beginning of execlists_context_unqueue(). Reported-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NMichel Thierry <michel.thierry@intel.com> Reviewed-by: NJani Nikula <jani.nikula@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Chris Wilson 提交于
In commit 1854d5ca Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Tue Apr 7 16:20:32 2015 +0100 drm/i915: Deminish contribution of wait-boosting from clients we removed an atomic timer based check for allowing waitboosting and moved it below the mutex taken during RPS. However, that mutex can be held for long periods of time on Vallyview/Cherryview as communication with the PCU is slow. As clients may frequently wait for results (e.g. such as tranform feedback) we introduced contention between the client and the RPS worker. We can take advantage of the RPS worker, by switching the wait boost decision to use spin locks and defer the actual reclocking to the worker. Fixes a regression of up to 45% on Baytrail and Baswell! v2 (Daniel): - Use max_freq_softlimit instead of the not-yet-merged boost frequency. - Don't inject a fake irq into the boost work, instead treat client_boost as just another legit waker. v3: Drop the now unused mask (Chris). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90112 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 26 5月, 2015 16 次提交
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由 Damien Lespiau 提交于
It was reported that this comment was confusing, and indeed it is. v2: (one year later!) Add the range for the DRM_I915_* iotcl defines (Daniel) Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Alex Deucher 提交于
Since we are messing with state in the worker. v2: drop the changes in the mst worker Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Joe Perches 提交于
Use the generic mechanism to declare a bitmap instead of unsigned long. Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Some of the vce clocks are automatic, others need to be manually enabled. For ease, just disable cg when vce is active. v2: rebased, call vce_v1_0_enable_mgcg directly Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Initial support for VCE 1.0 using newest firmware. v2: rebased v3: fix for TN v4: fix FW size calculation Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
This implements the function to set the vce clocks on TN hardware. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
For setting clocks with VCE v1.0 v2: (chk) rebased on current tree Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
They seem to work fine with the kernel interface. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Previously we were completely over allocating, fix this by actually implementing the size calculation. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Marek Olšák 提交于
Userspace will be able to tell whether a GPU reset occured by comparing an old referece value of the counter with a new value. Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NMarek Olšák <marek.olsak@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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git://linuxtv.org/pinchartl/fbdev由 Dave Airlie 提交于
adv7511 fix. * 'drm/next/adv7511' of git://linuxtv.org/pinchartl/fbdev: drm: adv7511: Fix crash in IRQ handler when no encoder is associated
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git://linuxtv.org/pinchartl/fbdev由 Dave Airlie 提交于
rcar-du fixes * 'drm/next/rcar-du' of git://linuxtv.org/pinchartl/fbdev: drm: rcar-du: Split planes pre-association 4/4 between CRTCs drm: rcar-du: Store the number of CRTCs per group in the group structure drm: rcar-du: Consider plane to CRTC associations in the plane allocator drm: rcar-du: Keep plane to CRTC associations when disabling a plane drm: rcar-du: Add plane allocation debugging drm: rcar-du: Rename to_rcar_du_plane_state to to_rcar_plane_state drm: rcar-du: Embed rcar_du_planes structure into rcar_du_group drm: rcar-du: Move properties from rcar_du_planes to rcar_du_device drm: rcar-du: Document the rcar_du_plane_state structure drm: rcar-du: Document the rcar_du_crtc structure
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