- 21 2月, 2015 1 次提交
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由 Arun Chandran 提交于
This patch converts all __raw_readl and __raw_writel function calls to their corresponding readl_relaxed and writel_relaxed variants. It also tells the driver to set ahb_endian_swp_mgmt_en bit in dma_cfg when the CPU is configured in big endian mode. Signed-off-by: NArun Chandran <achandran@mvista.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 16 1月, 2015 1 次提交
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由 Xander Huff 提交于
Change comments to not exceed 80 characters per line. Update block comments in macb.h to start on the line after /*. Signed-off-by: NXander Huff <xander.huff@ni.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 1月, 2015 2 次提交
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由 Xander Huff 提交于
Currently `ethtool -S` simply returns "no stats available". It would be more useful to see what the various ethtool statistics registers' values are. This change implements get_ethtool_stats, get_strings, and get_sset_count functions to accomplish this. Read all GEM statistics registers and sum them into macb.ethtool_stats. Add the necessary infrastructure to make this accessible via `ethtool -S`. Update gem_update_stats to utilize ethtool_stats. Signed-off-by: NXander Huff <xander.huff@ni.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Xander Huff 提交于
This change is to help improve at-a-glace knowledge of the purpose of the various Cadence MACB/GEM registers. Comments are more helpful for human readability than short acronyms. Describe various #define varibles Cadence MACB/GEM registers as documented in Xilinix's "Zynq-7000 All Programmable SoC TechnicalReference Manual, v1.9.1 (UG-585)" Signed-off-by: NXander Huff <xander.huff@ni.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 13 12月, 2014 1 次提交
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由 Cyrille Pitchen 提交于
gem devices designed with multiqueue CANNOT work without this patch. When probing a gem device, the driver must first prepare and enable the peripheral clock before accessing I/O registers. The second step is to read the MID register to find whether the device is a gem or an old macb IP. For gem devices, it reads the Design Configuration Register 6 (DCFG6) to compute to total number of queues, whereas macb devices always have a single queue. Only then it can call alloc_etherdev_mq() with the correct number of queues. This is the reason why the order of some initializations has been changed in macb_probe(). Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized for each queue. For backward compatibility reasons, queue0 uses the legacy registers ISR, IER, IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7]. Except this hardware detail there is no real difference between queue0 and the others. The driver hides that thanks to the struct macb_queue. This structure allows us to share a common set of functions for all the queues. Besides when a TX error occurs, the gem MUST be halted before writing any of the TBQP registers to reset the relevant queue. An immediate side effect is that the other queues too aren't processed anymore by the gem. So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux network engine that all transmissions are stopped. Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the interrupt handlers of the other queues from running as each of them may wake its associated queue up (please refer to macb_tx_interrupt()). Finally, as all queues have previously been stopped, they should be restarted calling netif_tx_start_all_queues() and setting the TSTART bit into the Network Control Register. Before this patch, when dealing with a single queue, the driver used to defer the reset of the faulting queue and the write of the TSTART bit until the next call of macb_start_xmit(). As explained before, this bit is now set by macb_tx_error_task() too. That's why the faulting queue MUST be reset by setting the TX_USED bit in its first buffer descriptor before writing the TSTART bit. Queue 0 always exits and is the lowest priority when other queues are available. The higher the index of the queue is, the higher its priority is. When transmitting frames, the TX queue is selected by the skb->queue_mapping value. So queue discipline can be used to define the queue priority policy. Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 25 7月, 2014 3 次提交
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由 Cyrille Pitchen 提交于
When RX checksum offload is enabled at GEM level (bit 24 set in the Network Control Register), frames with invalid IP, TCP or UDP checksums are discarted even if promiscuous mode is enabled (bit 4 set in the Network Control Register). This was verified with a simple userspace program, which corrupts UDP checksum using libnetfilter_queue. Then both IFF_PROMISC bit must be clear in dev->flags and NETIF_F_RXCSUM bit must be set in dev->features to enable RX checksum offload at GEM level. This way tcpdump is still able to capture corrupted frames. Also skb->ip_summed is set to CHECKSUM_UNNECESSARY only when both TCP/IP or UDP/IP checksums were verified by the GEM. Indeed the GEM may verify only IP checksum but not the one for ICMP (or other protocol than TCP or UDP). Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Cyrille Pitchen 提交于
The scatter-gather feature will allow to enable the Generic Segmentation Offload. Generic Segmentation Offload can be enabled/disabled using ethtool -K DEVNAME gso on|off. e.g: ethtool -K eth0 gso off When enabled, the driver may be provided with socket buffers splitted into many fragments. These fragments need to be queued into the TX ring in reverse order, starting from to the last one down to the first one, to avoid a race condition with the MAC. Especially the 'TX_USED' bit in word 1 of the transmit buffer descriptor of the first fragment should be cleared at the very final step of the queueing algorithm. This will tell the hardware that fragments are ready to be sent. Also since the MAC only update the status word of the first buffer descriptor of the ethernet frame, the queueing algorithm can no longer expect a 'TX_USED' bit to be set by the MAC into the buffer descriptor following the one for last fragment of the skb. This is why the driver sets the 'TX_USED' bit before queueing any fragment, so the end of queue position is well defined for the MAC. Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Nicolas Ferre 提交于
This addition will also allow to configure DMA burst length. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Acked-by: NCyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 11 12月, 2013 1 次提交
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由 Soren Brinkmann 提交于
Adjust the ethernet clock according to the negotiated link speed. Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 07 6月, 2013 2 次提交
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由 Nicolas Ferre 提交于
GEM is able to adapt its DMA buffer size, so change the RX path to take advantage of this possibility and remove all kind of memcpy in this path. This modification introduces function pointers for managing differences between MACB and GEM adapter type. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Nicolas Ferre 提交于
Macb Ethernet controller requires a RX buffer of 128 bytes. It is highly sub-optimal for Gigabit-capable GEM that is able to use a bigger DMA buffer. Change this constant and associated macros with data stored in the private structure. RX DMA buffer size has to be multiple of 64 bytes as indicated in DMA Configuration Register specification. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 15 5月, 2013 1 次提交
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由 Nicolas Ferre 提交于
Commit 749a2b66 (net/macb: clear tx/rx completion flags in ISR) introduces clear-on-write on ISR register. This behavior is not always implemented when using Cadence MACB/GEM and is breaking other platforms. We are using the Design Configuration Register 1 information and a capability property to actually activate this clear-on-write behavior on ISR. Reported-by: NHein Tibosch <hein_tibosch@yahoo.es> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NHein Tibosch <hein_tibosch@yahoo.es> Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 29 3月, 2013 1 次提交
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由 Steffen Trumtrar 提交于
The core has a bit for swapping packet data endianism. Reset default from Cadence is off. Xilinx however, who uses this core on the Zynq SoCs, opted for on. Force it to off. This shouldn't change the behaviour for current users of the macb, but enables usage on Zynq devices. Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 24 11月, 2012 1 次提交
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由 Nicolas Ferre 提交于
Add information to the DMA Configuration Register to maximize system performance: - rx/tx packet buffer full memory size - allow possibility to use INCR16 if supported Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Joachim Eastwood <manabian@gmail.com Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 15 11月, 2012 1 次提交
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由 Joachim Eastwood 提交于
Only the first register set is used for matching but we support getting the initial hw addr from any of the registers. To prevent stale entries and false matches clear unused register sets. This most important for the at91_ether driver where u-boot always uses the 2nd register set. Signed-off-by: NJoachim Eastwood <manabian@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 08 11月, 2012 3 次提交
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由 Joachim Eastwood 提交于
No longer used after gpio phy interrupt support was removed from at91_ether. Signed-off-by: NJoachim Eastwood <manabian@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Joachim Eastwood 提交于
Signed-off-by: NJoachim Eastwood <manabian@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Joachim Eastwood 提交于
for usage in at91_ether driver. Signed-off-by: NJoachim Eastwood <manabian@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 01 11月, 2012 4 次提交
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由 Nicolas Ferre 提交于
Handle all TX errors, not only underruns. TX error management is deferred to a dedicated workqueue. Reinitialize the TX ring after treating all remaining frames, and restart the controller when everything has been cleaned up properly. Napi is not stopped during this task as the driver only handles napi for RX for now. With this sequence, we do not need a special check during the xmit method as the packets will be caught by TX disable during workqueue execution. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NJoachim Eastwood <manabian@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Nicolas Ferre 提交于
Add macb_get_regs() ethtool function and its helper function: macb_get_regs_len(). The version field is deduced from the IP revision which gives the "MACB or GEM" information. An additional version field is reserved. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Reviewed-by: NBen Hutchings <bhutchings@solarflare.com> Tested-by: NJoachim Eastwood <manabian@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Havard Skinnemoen 提交于
Instead of masking head and tail every time we increment them, just let them wrap through UINT_MAX and mask them when subscripting. Add simple accessor functions to do the subscripting properly to minimize the chances of messing this up. This makes the code slightly smaller, and hopefully faster as well. Also, doing the ring buffer management this way will simplify things a lot when making the ring sizes configurable in the future. Available number of descriptors in ring buffer function by David Laight. Signed-off-by: NHavard Skinnemoen <havard@skinnemoen.net> [nicolas.ferre@atmel.com: split patch in topics, adapt to newer kernel] Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NJoachim Eastwood <manabian@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Patrice Vilchez 提交于
Add Gigabit Ethernet mode to GEM cadence IP and enable RGMII connection. Signed-off-by: NPatrice Vilchez <patrice.vilchez@atmel.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NJoachim Eastwood <manabian@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 20 10月, 2012 8 次提交
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由 Joachim Eastwood 提交于
This patch does two things: * Use macb struct members and remove at91_ether ones * Alloc DMA buffers on netdev start and dealloc on stop Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
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由 Joachim Eastwood 提交于
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
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由 Joachim Eastwood 提交于
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
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由 Joachim Eastwood 提交于
This rips out the at91_ether phy handling and ethtool stuff and replace it with equivalent stuff from macb. The only thing lost is the phy irq support from at91_ether, but this can be added to macb and then benefit all users. Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
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由 Joachim Eastwood 提交于
Export some symbols to start sharing code between macb and at91_ether drivers. Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
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由 Joachim Eastwood 提交于
Remove old at91_priv member and use pclk member from macb. Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
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由 Joachim Eastwood 提交于
This will make it easier to share code between the drivers and eventually merge them into one driver. Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
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由 Joachim Eastwood 提交于
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
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- 16 12月, 2011 1 次提交
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Allow the device tree to provide the mac address and the phy mode. Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> [nicolas.ferre@atmel.com: change "compatible" node property, doc and DT hwaddr] Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> [jamie@jamieiles.com: add "gem" compatibility strings and doc] Acked-by: Jamie Iles<jamie@jamieiles.com> Acked-by: NDavid S. Miller <davem@davemloft.net>
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- 22 11月, 2011 5 次提交
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由 Jamie Iles 提交于
GEM has configurable receive buffer sizes so requires this to be programmed up. Any size < 2048 and a multiple of 64 bytes is permitted. Signed-off-by: NJamie Iles <jamie@jamieiles.com> Acked-by: NDavid S. Miller <davem@davemloft.net> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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由 Jamie Iles 提交于
Some GEM implementations may support DMA bus widths up to 128 bits. We can get the maximum supported DMA bus width from the design configuration register so use that to program the device up. Signed-off-by: NJamie Iles <jamie@jamieiles.com> Acked-by: NDavid S. Miller <davem@davemloft.net> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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由 Jamie Iles 提交于
GEM devices have a different number of statistics registers and they are at a different offset to MACB devices. Make the statistics collection method dependent on device type. Signed-off-by: NJamie Iles <jamie@jamieiles.com> Acked-by: NDavid S. Miller <davem@davemloft.net> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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由 Jamie Iles 提交于
GEM devices support larger clock divisors and have a different range of divisors. Program the MDIO clock divisors based on the device type. Signed-off-by: NJamie Iles <jamie@jamieiles.com> Acked-by: NDavid S. Miller <davem@davemloft.net> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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由 Jamie Iles 提交于
The Cadence GEM is based on the MACB Ethernet controller but has a few small changes with regards to register and bitfield placement. This patch detects the presence of a GEM by reading the module ID register and setting a flag appropriately. This handles the new HW address, USRIO and hash register base register locations in GEM. v3: - convert to macb_is_gem() inline rather than storing a boolean flag - handle rx_overrun stats for gem Acked-by: NDavid S. Miller <davem@davemloft.net> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NJamie Iles <jamie@jamieiles.com> Tested-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 13 8月, 2011 1 次提交
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由 Jeff Kirsher 提交于
Move the Atmel driver into drivers/net/ethernet/cadence/ and make the necessary Kconfig and Makefile changes. CC: Nicolas Ferre <nicolas.ferre@atmel.com> CC: Jamie Iles <jamie@jamieiles.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com> Acked-by: NJamie Iles <jamie@jamieiles.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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- 09 10月, 2008 1 次提交
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由 Lennert Buytenhek 提交于
This patch introduces mdiobus_alloc() and mdiobus_free(), and makes all mdio bus drivers use these functions to allocate their struct mii_bus'es dynamically. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net> Acked-by: NAndy Fleming <afleming@freescale.com>
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- 11 10月, 2007 1 次提交
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由 Stephen Hemminger 提交于
Several devices have multiple independant RX queues per net device, and some have a single interrupt doorbell for several queues. In either case, it's easier to support layouts like that if the structure representing the poll is independant from the net device itself. The signature of the ->poll() call back goes from: int foo_poll(struct net_device *dev, int *budget) to int foo_poll(struct napi_struct *napi, int budget) The caller is returned the number of RX packets processed (or the number of "NAPI credits" consumed if you want to get abstract). The callee no longer messes around bumping dev->quota, *budget, etc. because that is all handled in the caller upon return. The napi_struct is to be embedded in the device driver private data structures. Furthermore, it is the driver's responsibility to disable all NAPI instances in it's ->stop() device close handler. Since the napi_struct is privatized into the driver's private data structures, only the driver knows how to get at all of the napi_struct instances it may have per-device. With lots of help and suggestions from Rusty Russell, Roland Dreier, Michael Chan, Jeff Garzik, and Jamal Hadi Salim. Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra, Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan. [ Ported to current tree and all drivers converted. Integrated Stephen's follow-on kerneldoc additions, and restored poll_list handling to the old style to fix mutual exclusion issues. -DaveM ] Signed-off-by: NStephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 17 7月, 2007 1 次提交
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由 frederic RODO 提交于
Convert the macb driver to use the generic PHY layer in drivers/net/phy. Signed-off-by: NFrederic RODO <f.rodo@til-technologies.fr> Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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