Adding the PM configuration of PMC when the platform support suspend
function.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This patch adds "non-removable" property of MMC host where the eMMC device
is for Tegra platform.

And the "keep-power-in-suspend" property was used for the SDIO device that
need this to go into suspend mode (e.g. BRCM43xx series).
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding KBC as a wakeup source for Whistler board.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This adds the power gpio key to DT and enable the wakeup of the gpio key
for the device. The Seaboard and paz00 already had the power gpio key
binding and the power key of Whistler was on KBC. So these boards' device
tree didn't include in this patch.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Set "regulator-always-on" for the SD slot on Dalmore, so that SD cards
work. This used to work, since this regulator is on by default, but was
broken by commit "ARM: tegra: dalmore: add TPS65090 node", since that
didn't specify always-on for this regulator.

In the long run, the regulators should all be hooked up to the SDHCI
device nodes. However, we haven't done that for any of the Tegra boards
yet, so to be consistent, this patch simply forces the regulator on,
rather than hooking it up and making it work differently to other boards.
Reported-by: NRhyland Klein <rklein@nvidia.com>
Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Audio-related clocks need to be represented in the device tree. Update
bindings to describe which clocks are needed, and DT files to include
those clocks.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Audio-related clocks need to be represented in the device tree. Update
bindings to describe which clocks are needed, and DT files to include
those clocks.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

NVIDIA's Tegra114 reference platform Dalmore has voltage switch
regulators which are controlled by the Tegra GPIOs.

Add DT node for fixed regulators.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

NVIDIA's Tegra114 reference platform, Dalmore, uses the TPS65090 as
secondary PMICs which is mainly act as voltage switch regulator
controlled by i2c communication.

Add DT node for TPS65090.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: remove unit-address from node name since it's unique already]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Dalmore uses the TPS51632 as CPU regulator. The device is connected
on I2C5.

Add DT node for TPS51632.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This patch adds the node for the bq20z45 I2C gas gauge which is
compatible with the sbs-battery power supply driver.
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
[swarren: remove unit-address from node name since it's unique already]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

NVIDIA's Tegra114 has 6 SPI controllers. These controllers are
redesign on T114 with different register interface.

Add DT entry for spi controllers and make it compatible with
"nvidia,tegra114-spi", since they are a new incompatible design.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed reg property for 3rd SPI controller]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
supports 11x8 type of matrix. The number of rows and columns
are configurable.

Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc".
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add APB DMA requestor and serial aliases for serial controller.
There are two serial drivers i.e. 8250 based simple serial driver
and APB DMA based serial driver for higher baudrate and performace.

The simple serial driver is selected by compatible value
"nvidia,tegra114-uart", "nvidia,tegra20-uart", and the APB DMA based
driver is selected by compatible value "nvidia,tegra114-hsuart",
"nvidia,tegra30-hsuart".
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

NVIDIA's Tegra114 has 5 I2C controllers. These controllers have the
following changes which makes incompatible with previous hardware:
- Single clock source to I2C controller.
- Interrupt support for per packet transfer.

Add DT entry for I2C controllers and make it compatible with
"nvidia,tegra114-i2c".
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed location of status property for consistency]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".

Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA
controller driver as in Tegra114, the global pause also clock gate the
DMA register and hence it iw not possible to write the DMA register
with global pause.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed DT node order]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This patch adds a device tree node for the four PWM controllers present
on Tegra114.
Signed-off-by: NAndrew Chew <achew@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

We should be defining the PWM nodes with status as "disabled" in the
chip-specific dtsi file, since we don't know whether specific boards
will use the PWM or not. This patch fixes the PWM node status for
Tegra20 and Tegra30.

Also fixed the one user of PWM, which is the Tegra20 medcom-wide board,
so that PWM is set to "okay" in the board-specific dts file.
Signed-off-by: NAndrew Chew <achew@nvidia.com>
[swarren: in medcom-wide: fixed node sort order, removed duplicate pwm:
label, fixed syntax error]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Dalmore has a built-in eMMC device and a user-accessible SD card slot.
Add device tree nodes to enable these.

Based on changes by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
[swarren: added commit description, fixed DT node sort order]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This patch adds in the SDHCI nodes for the busses supported on Tegra114
boards.
Signed-off-by: NPritesh Raithatha <praithatha@nvidia.com>
[Rhyland added clk refs to & reordered sdhci nodes and removed spaces]
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
[swarren: fixed DT node sort order]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This change adds the default pinctrl nodes for the Dalmore Tegra114
platform.
Signed-off-by: NPritesh Raithatha <praithatha@nvidia.com>
[Rhyland added patch description]
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
[swarren: fixed DT node sort order]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The USB PHY nodes are all grouped together rather than being sorted based
on reg address like all other nodes fix this.

I apologize for the churn; I should have noticed this during review of the
patches that caused this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Remove white-space from empty line; triggers checkpatch.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add references to tegra_car clocks for the basic device nodes. Also remove
the clock-frequency property of the serial node as the UART driver can now
use the clock framework to obtain the frequency.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is required. It can't be initialized later, since the .init_timer()
hook needs the clocks initialized. However, at this time, udelay()
doesn't work.

The Tegra clock initialization table may enable some PLLs. Enabling a PLL
may require usage of udelay(). Hence, this can't happen right when the
clock driver is initialized.

To solve this, separate the clock driver initialization from the clock
table processing, so they can execute at separate times.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

After the patch series for system suspending support, tegra_idle_lp2_last()
no longer uses its parameters cpu_on_time or cpu_off_time, so remove them.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding suspend to RAM support for Tegra platform. There are three suspend
mode for Tegra. The difference were below.

* LP2: CPU voltage off
* LP1: CPU voltage off, DRAM in self-refresh
* LP0: CPU + Core voltage off, DRAM in self-refresh

After this patch, the LP2 suspend mode will be supported.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The PMC mostly controls the entry and exit of the system from different
sleep modes. Different platform or system may have different configurations.
The power management configurations of PMC is represented as some properties.
The system needs to define the properties when the system supports deep sleep
mode (i.e. suspend).

Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the wake up handling for legacy irq controller, and using
IRQCHIP_MASK_ON_SUSPEND for wake irq handling.

Based on the work by:
Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The CPU power timer set up function was related to PMC register. Now moving
it to PMC driver. And it also help to clean up the PM related code later.

The timer was calculated based on the input clock of PMC. In this patch, we
also get the clock from DT.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding the bindings of the clock source of PMC in DT.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Commit ce4f3313 (clk: add table lookup to mux) caused the following build
error on imx_v4_v5_defconfig/imx_v6_v7_defconfig:

arch/arm/mach-imx/clk-busy.c:172:11: error: 'struct clk_mux' has no member named 'width'

Fix it by passing the 'mask' field.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: shortened $SUBJECT line]

Add speedo-based process identification for Tegra114.

Based on the work by: Alex Frid <afrid@nvidia.com>
Signed-off-by: NDanny Huang <dahuang@nvidia.com>
[swarren: added include of bug.h]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

887cbce0 "arch Kconfig: centralise CONFIG_ARCH_NO_VIRT_TO_BUS"
and  4febd95a "Select VIRT_TO_BUS directly where needed" from
Stephen Rothwell changed globally how CONFIG_VIRT_TO_BUS is
selected, while my own a5d533ee "ARM: disable virt_to_bus/
virt_to_bus almost everywhere" was merged at the same time and
changed which platforms select it on ARM.

The result of this conflict was that we again see CONFIG_VIRT_TO_BUS
on all ARM systems. This patch fixes up the problem and removes
CONFIG_ARCH_NO_VIRT_TO_BUS again on ARM.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>

Expose Tegra chip ID and revision in /sys/devices/soc for user mode
usage
Signed-off-by: NDanny Huang <dahuang@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

With recent arm broadcast time clean-up from Mark Rutland, the dummy
broadcast device is always registered with timer subsystem. And since
the rating of the dummy clock event is very high, it may be preferred
over a real clock event.

This is a change in behavior from past and not an intended one. So
reduce the rating of the dummy clock-event so that real clock-event
device is selected when available.
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The i.MX35 has two bits per clock gate which are decoded as follows:
      0b00 -> clock off
      0b01 -> clock is on in run mode, off in wait/doze
      0b10 -> clock is on in run/wait mode, off in doze
      0b11 -> clock is always on

The reset value for the MAX clock is 0b10.

The MAX clock is needed by the SoC, yet unused in the Kernel, so the
common clock framework will disable it during late init time. It will
only disable clocks though which it detects as being turned on. This
detection is made depending on the lower bit of the gate. If the reset
value has been altered by the bootloader to 0b11 the clock framework
will detect the clock as turned on, yet unused, hence it will turn it
off and the system locks up.

This patch turns the MAX clock on unconditionally making the Kernel
independent of the bootloader.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Scorpion processors have always been v7 CPUs. Fix the Kconfig
text to reflect this.
Reported-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

arch/arm/mach-mmp/gplugd.c: In function ‘gplugd_init’:
arch/arm/mach-mmp/gplugd.c:188:2: error: implicit declaration of
function ‘platform_device_register’
[-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors
make[1]: *** [arch/arm/mach-mmp/gplugd.o] Error 1
make: *** [arch/arm/mach-mmp] Error 2

So append platform_device.h to resolve build issue.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>

56bc911a "[media] s5p-fimc: Redefine platform data structure for fimc-is"
changed the bus_type member of struct fimc_source_info treewide, but
got one instance wrong in mach-s5pv210, which was evidently not
even build tested.

This adds the missing change to get s5pv210_defconfig to build again.
Applies on the Mauro's media tree.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Mauro Carvalho Chehab <mchehab@redhat.com>