Some of the vce clocks are automatic, others need to
be manually enabled.  For ease, just disable cg when
vce is active.

v2: rebased
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The adds the appropriate function calls to properly re-init
vce before it's used after it has been power gated.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

TODO: plug in cik_vce_suspend()/resume() so we can enable
vce powergating. See XXX in code.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

It's needed by by both the asic specific functions and the
extended table parser.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If we take the false branch of the if quoted in the diff below, we
end up doing a return ret, without ever having initialized it.

Picked up by coverity.
Signed-off-by: NDave Jones <davej@fedoraproject.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Right now it's called right after enable, but after
reworking the dpm init order, it will get called later
to accomodate loading the smc early, but enabling
thermal interrupts and block powergating later after
the ring tests are complete.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd, etc. until after
the ring tests.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

I'm not entirely sure this is required and it won't work
with the dpm restructing anyway.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

May cause stability problems on some boards.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Calling force_performance_level() from set_power_state()
doesn't work on some asics because the current power
state pointer has not been properly updated at that point.
Move the calls to force_performance_level() out of the
asic specific set_power_state() functions and into
the main power state sequence.

Fixes dpm resume on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds the enable_bapm callback for kb/kv.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

bapm is a power management feature for handling the
power budget between the CPU and GPU on APUs.  This
patch adds support for enabling or disabling it.
For now disable it by default.  Enabling it properly
requires quite a bit more work and will be addressed
in a separate patch.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This updates dpm support for KV asics. Notably there
are some changes in acp handling and forcing performance
levels.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The problem here is that "unsigned i" is always greater than or equal to
zero.  These loops mostly have a second check for "(i == 0)" so only the
last two are actually buggy.  The rest is just cleanup.

Bug 1:  kv_force_dpm_highest() doesn't have an "(i == 0)" check so it's
a potential forever loop.

Bug 2: In kv_get_sleep_divider_id_from_clock() there is a typo and the
test is reversed "<=" vs ">" so we never enter the loop.  That means
normally we return KV_MAX_DEEPSLEEP_DIVIDER_ID (5).  The return value
from here is saved in ->DeepSleepDivId and I wasn't able to determine
how that is used.  This is a static checker fix and I have not tested
it.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs.  Rather than indexing the arrays, use
pointer arithmetic.

See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Avoid needless uvd reprogramming if uvd powergating is disabled.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

These blocks need to be ungated for the other parts of
the driver properly initialize them (e.g., after a gpu
reset, etc.).
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Clockgating needs to be disabled around certain parts
of dpm setup otherwise the smc gets into a bad state
and dpm doesn't work properly.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Our different hardware blocks are actually completely
separated, so it doesn't make much sense any more to
structure the code by pure chipset generations.

Start restructuring the code by separating our the UVD block.

v2: updated commit message
v3: rebased and restructurized start/stop functions for kv dpm.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Powergate the UVD block when not in use to save power.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows you to force the selected performance level via sysfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This allows you to look at the current DPM state via
debugfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for KB/KV asics.  This includes:
- dynamic engine clock scaling
- dynamic voltage scaling
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>