1. 01 8月, 2015 2 次提交
    • W
      ARM: 8407/1: switch_to: Remove finish_arch_switch · 9ac87c5a
      Will Deacon 提交于
      Fold finish_arch_switch() into switch_to(), in preparation for the
      removal of the finish_arch_switch call from core sched code.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      9ac87c5a
    • S
      ARM: 8392/3: smp: Only expose /sys/.../cpuX/online if hotpluggable · 787047ee
      Stephen Boyd 提交于
      Writes to /sys/.../cpuX/online fail if we determine the platform
      doesn't support hotplug for that CPU. Furthermore, if the cpu_die
      op isn't specified the system hangs when we try to offline a CPU
      and it comes right back online unexpectedly. Let's figure this
      stuff out before we make the sysfs nodes so that the online file
      doesn't even exist if it isn't (at least sometimes) possible to
      hotplug the CPU.
      
      Add a new 'cpu_can_disable' op and repoint all 'cpu_disable'
      implementations at it because all implementers use the op to
      indicate if a CPU can be hotplugged or not in a static fashion.
      With PSCI we may need to add a 'cpu_disable' op so that the
      secure OS can be migrated off the CPU we're trying to hotplug.
      In this case, the 'cpu_can_disable' op will indicate that all
      CPUs are hotpluggable by returning true, but the 'cpu_disable' op
      will make a PSCI migration call and occasionally fail, denying
      the hotplug of a CPU. This shouldn't be any worse than x86 where
      we may indicate that all CPUs are hotpluggable but occasionally
      we can't offline a CPU due to check_irq_vectors_for_cpu_disable()
      failing to find a CPU to move vectors to.
      
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Nicolas Pitre <nico@linaro.org>
      Cc: Dave Martin <Dave.Martin@arm.com>
      Acked-by: Simon Horman <horms@verge.net.au> [shmobile portion]
      Tested-by: NSimon Horman <horms@verge.net.au>
      Cc: Magnus Damm <magnus.damm@gmail.com>
      Cc: <linux-sh@vger.kernel.org>
      Tested-by: NTyler Baker <tyler.baker@linaro.org>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      787047ee
  2. 10 7月, 2015 3 次提交
    • W
      ARM: 8403/1: kbuild: don't use generic mcs_spinlock.h header · 57853e89
      Will Deacon 提交于
      We provide our own implementation of asm/mcs_spinlock.h, so there's no
      need to ask for the (empty) generic version.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      57853e89
    • S
      ARM: 8401/1: perf: Set affinity for PPI based PMUs · 8ded1e1a
      Stephen Boyd 提交于
      For PPI based PMUs, we bail out early in of_pmu_irq_cfg() without
      setting the PMU's supported_cpus bitmap. This causes the
      smp_call_function_any() in armv7_probe_num_events() to fail. Set
      the bitmap to be all CPUs so that we properly probe PMUs that use
      PPIs.
      
      Fixes: cc88116d ("arm: perf: treat PMUs as CPU affine")
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      8ded1e1a
    • G
      ARM: 8395/1: l2c: Add support for the "arm,shared-override" property · eeedcea6
      Geert Uytterhoeven 提交于
      "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
      Shareable attribute" states:
      
          "The default behavior of the cache controller with respect to the
           shareable attribute is to transform Normal Memory Non-cacheable
           transactions into:
              - cacheable no allocate for reads
              - write through no write allocate for writes."
      
      Depending on the system architecture, this may cause memory corruption
      in the presence of bus mastering devices (e.g. OHCI). To avoid such
      corruption, the default behavior can be disabled by setting the Shared
      Override bit in the Auxiliary Control register.
      
      Currently the Shared Override bit can be set only using C code:
        - by calling l2x0_init() directly, which is deprecated,
        - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
          fields, but using values differing from 0/~0 is also deprecated.
      
      Hence add support for an "arm,shared-override" device tree property for
      the l2c device node. By specifying this property, affected systems can
      indicate that non-cacheable transactions must not be transformed.
      Then, it's up to the OS to decide. The current behavior is to set the
      "shared attribute override enable" bit, as there may exist kernel linear
      mappings and cacheable aliases for the DMA buffers, even if CMA is
      enabled.
      
      See also commit 1a8e41cd ("ARM: 6395/1: VExpress: Set bit 22 in
      the PL310 (cache controller) AuxCtlr register"):
      
          "Clearing bit 22 in the PL310 Auxiliary Control register (shared
           attribute override enable) has the side effect of transforming
           Normal Shared Non-cacheable reads into Cacheable no-allocate reads.
      
           Coherent DMA buffers in Linux always have a Cacheable alias via the
           kernel linear mapping and the processor can speculatively load
           cache lines into the PL310 controller. With bit 22 cleared,
           Non-cacheable reads would unexpectedly hit such cache lines leading
           to buffer corruption."
      Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      eeedcea6
  3. 06 7月, 2015 2 次提交
    • L
      Linux 4.2-rc1 · d770e558
      Linus Torvalds 提交于
      d770e558
    • L
      Merge tag 'platform-drivers-x86-v4.2-2' of... · a585d2b7
      Linus Torvalds 提交于
      Merge tag 'platform-drivers-x86-v4.2-2' of git://git.infradead.org/users/dvhart/linux-platform-drivers-x86
      
      Pull late x86 platform driver updates from Darren Hart:
       "The following came in a bit later and I wanted them to bake in next a
        few more days before submitting, thus the second pull.
      
        A new intel_pmc_ipc driver, a symmetrical allocation and free fix in
        dell-laptop, a couple minor fixes, and some updated documentation in
        the dell-laptop comments.
      
        intel_pmc_ipc:
         - Add Intel Apollo Lake PMC IPC driver
      
        tc1100-wmi:
         - Delete an unnecessary check before the function call "kfree"
      
        dell-laptop:
         - Fix allocating & freeing SMI buffer page
         - Show info about WiGig and UWB in debugfs
         - Update information about wireless control"
      
      * tag 'platform-drivers-x86-v4.2-2' of git://git.infradead.org/users/dvhart/linux-platform-drivers-x86:
        intel_pmc_ipc: Add Intel Apollo Lake PMC IPC driver
        tc1100-wmi: Delete an unnecessary check before the function call "kfree"
        dell-laptop: Fix allocating & freeing SMI buffer page
        dell-laptop: Show info about WiGig and UWB in debugfs
        dell-laptop: Update information about wireless control
      a585d2b7
  4. 05 7月, 2015 33 次提交