- 20 4月, 2009 7 次提交
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由 Paul Mundt 提交于
Not all PCI channels have non-translatable memory windows, this is a special property of the on-chip PCIC with its 0xfd00... mapping, handle this explicitly. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
This consolidates the pci_iomap() definitions and reworks how the I/O port base is handled. PCI channels can register their own I/O map base, or if none is provided, the system-wide generic I/O base is used instead. Functionally nothing changes, while this allows us to kill off lots of I/O address special casing and lookups. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
This is left over cruft that hasn't been used by anything in a long time, kill off bits that weren't purged previously. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
This introduces a saner pcibios_align_resource() that can be used regardless of whether pci-auto or pci-new are being used, and consolidates it in pci-lib.c. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
Derived from the MIPS version, now uses pgprot_noncached(). Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
This splits off a 'pci-new.c' which is aimed at gradually replacing the pci-auto backend and the arch/sh/drivers/pci/pci.c core respectively. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
The new PCI code wants its own bus<->resource mappings instead of the generic equivalents, so drop the asm-generic include in preparation. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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- 17 4月, 2009 12 次提交
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由 Paul Mundt 提交于
This starts moving out the common initialization bits from the various fixup paths in to the shared init path. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
Now that the platform code is a bit leaner, we can start consolidating the various IRQ routing implementations. There are effectively only 2 variants, and the others can use those directly. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
Commit 68b42d1b ("sh: sh7785lcr: Map whole PCI address space.") changed around the semantics of how various chip-selects are made accessible to PCI. Now that there is a single large mapping covering from CS0-CS6, there is no longer any need to do multi-window mapping. Subsequently, all of the differing implementations can be consolidated in to pci-sh7780. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
This consolidates all of the PCI I/O and memory window definitions across the pci-sh7780 users in pci-sh7780 itself. No functional changes, in that every platform had exactly the same implementation. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
Presently the I/O port base isn't being set anywhere, which allows things like generic_inl() to blow up. Fix this up to point at the PCI IO window. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
The SH7780 PCIC contains a read-only cache line size register that we can derive pci_cache_line_size from. So, make sure that the software idea of the cache line size actually matches the host controller's idea. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
Don't use pci_write_reg() for these, as it defaults to 32-bit. Rather than using the helper, use __raw_writeb() directly. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
This reworks how the host controller is probed, and makes it a bit more verbose in the event a new type of controller is detected. Additionally, we also log the revision information. This now uses the proper access sizes for the vendor/device registers, rather than relying on a larger access that encapsulated both of them. Not all devices support 32-bit read cycles for these registers. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
The SH7780 PCI host controller implements a configuration header that requires a fair bit of hand-holding to initialize properly. By default it appears as a pre-2.0 host controller given the zeroed out class code, so fix this up properly. Some boards that happened to be using the R7780RP version of the PCIC fixups had set this correctly, but this belongs in the standard initialization, and is by no means board specific. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
P1SEGADDR is obsolete and will be killed off completely in the future, so transition off of it and reference P1SEG explicitly. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
These fixups belong in the board INTC setup code, not in the middle of pci-sh7780.c. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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- 16 4月, 2009 13 次提交
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由 Paul Mundt 提交于
Nothing ended up using this anymore, so just kill it off. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
SE7780 has the same PCIC fixup as SDK7780, and SH7785LCR the same as R7780RP. Switch to using those, and drop the duplicate code. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Paul Mundt 提交于
With board_pci_channels now being exported in a single place, update the boards that duplicated the export. Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Magnus Damm 提交于
Instead of sometimes exporting board_pci_channels[] in the board specific code just export it in one place. Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Magnus Damm 提交于
Adds a __get_pci_io_base() function which is used to match a port range against struct pci_channel. This allows us to detect if a port range is assigned to pci or happens to be legacy port io. While at it, remove unused cpu-specific cruft. Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Magnus Damm 提交于
This patch changes the code to use __is_pci_memory() instead of is_pci_memaddr(). __is_pci_memory() loops through all the pci channels on the system to match memory windows. Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Magnus Damm 提交于
Store the io window base address in struct pci_channel and use that one instead of SH77xx_PCI_IO_BASE. Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Magnus Damm 提交于
Store the base address of the pci host controller registers in struct pci_channel and use the address in pci_read_reg() and pci_write_reg(). Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Magnus Damm 提交于
Store a struct pci_channel pointer in bus->sysdata. This makes whatever struct pci_channel assigned to a bus available for sh4_pci_read() and sh4_pci_write(). We also modify PCIBIOS_MIN_IO and PCIBIOS_MIN_MEM to use bus->sysdata - this to gives us support for multiple pci channels. Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Magnus Damm 提交于
Replaces PCIBIOS_MIN_IO and PCIBIOS_MIN_MEM with direct struct pci_channel access. This allows us to have more than one pci channel. Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Magnus Damm 提交于
This patch adds an init callback to struct pci_channel and makes sure it is initialized properly. Code is added to call this init function from pcibios_init(). Return values are adjusted and a warning is is printed if init fails. Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Magnus Damm 提交于
These patches rework the pci code for the sh architecture. Currently each board implements some kind of ioport to address mapping. Some boards use generic_io_base others try passing addresses as io ports. This is the first set of patches that try to unify the pci code as much as possible to avoid duplicated code. This will in the end lead to fewer lines board specific code and more generic code. This patch makes sure a struct pci_channel pointer is passed along to various pci functions such as pci_read_reg(), pci_write_reg(), pci_fixup_pcic(), sh7751_pcic_init() and sh7780_pcic_init(). Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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- 15 4月, 2009 6 次提交
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由 Linus Torvalds 提交于
It turns out that 'smp_call_function_many()' doesn't work at all like 'smp_call_function_single()', and my change to Andrew's patch to use it rather than a loop over all CPU's acpi-cpufreq doesn't work. My bad. 'smp_call_function_many()' has two "features" (aka "documented bugs"): (a) it needs to be called with preemption disabled, because it uses smp_processor_id() without guarding the CPU lookup with 'get_cpu()' and 'put_cpu()' like the 'single' variant does. (b) even if the current CPU is part of the CPU mask, it won't do the call on that CPU. Still, we're better off trying to use 'smp_call_function_many()' than looping over CPU's, since it at least in theory allows us to use a broadcast IPI and do it all in parallel. So let's just work around the silly semantic bugs in that function. Reported-and-tested-by: NAli Gholami Rudi <ali@rudi.ir> Cc: Ingo Molnar <mingo@elte.hu> Cc: Andrew Morton <akpm@linux-foundation.org>, Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Dave Jones <davej@redhat.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Sachin Sant 提交于
A randconfig build on powerpc failed with: dtl.c: In function 'dtl_init': dtl.c:238: error: implicit declaration of function 'firmware_has_feature' dtl.c:238: error: 'FW_FEATURE_SPLPAR' undeclared (first use in this function) - We need firmware.h for these definitions. Signed-off-by: NSachin Sant <sachinp@in.ibm.com> Signed-off-by: NJeremy Kerr <jk@ozlabs.org> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Paul Mackerras 提交于
Richard Henderson pointed out that the powerpc __futex_atomic_op has a bug: it will write the wrong value if the stwcx. fails and it has to retry the lwarx/stwcx. loop, since 'oparg' will have been overwritten by the result from the first time around the loop. This happens because it uses the same register for 'oparg' (an input) as it uses for the result. This fixes it by using separate registers for 'oparg' and 'ret'. Cc: stable@kernel.org Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Mike Mason 提交于
While adding native EEH support to Emulex and Qlogic drivers, it was discovered that dev->error_state was set to pci_io_channel_normal too late in the recovery process. These drivers rely on error_state to determine if they can access the device in their slot_reset callback, thus error_state needs to be set to pci_io_channel_normal in eeh_report_reset(). Below is a detailed explanation (courtesy of Richard Lary) as to why this is necessary. Background: PCI MMIO or DMA accesses to a frozen slot generate additional EEH errors. If the number of additional EEH errors exceeds EEH_MAX_FAILS the adapter will be shutdown. To avoid triggering excessive EEH errors and an undesirable adapter shutdown, some drivers use the pci_channel_offline(dev) wrapper function to return a Boolean value based on the value of pci_dev->error_state to determine if PCI MMIO or DMA accesses are safe. If the wrapper returns TRUE, drivers must not make PCI MMIO or DMA access to their hardware. The pci_dev structure member error_state reflects one of three values, 1) pci_channel_io_normal, 2) pci_channel_io_frozen, 3) pci_channel_io_perm_failure. Function pci_channel_offline(dev) returns TRUE if error_state is pci_channel_io_frozen or pci_channel_io_perm_failure. The EEH driver sets pci_dev->error_state to pci_channel_io_frozen at the point where the PCI slot is frozen. Currently, the EEH driver restores dev->error_state to pci_channel_io_normal in eeh_report_resume() before calling the driver's resume callback. However, when the EEH driver calls the driver's slot_reset callback() from eeh_report_reset(), it incorrectly indicates the error state is still pci_channel_io_frozen. Waiting until eeh_report_resume() to restore dev->error_state to pci_channel_io_normal is too late for Emulex and QLogic FC drivers and any other drivers which are designed to use common code paths in these two cases: i) those called after the driver's slot_reset callback() and ii) those called after the PCI slot is frozen but before the driver's slot_reset callback is called. Case i) all driver paths executed to reinitialize the hardware after a reset and case ii) all code paths executed by driver kernel threads that run asynchronous to the main driver thread, such as interrupt handlers and worker threads to process driver work queues. Emulex and QLogic FC drivers are designed with common code paths which require that pci_channel_offline(dev) reflect the true state of the hardware. The state transitions that the hardware takes from Normal Operations to Slot Frozen to Reset to Normal Operations are documented in the Power Architecture™ Platform Requirements+ (PAPR+) in Table 75. PE State Control. PAPR defines the following 3 states: 0 -- Not reset, Not EEH stopped, MMIO load/store allowed, DMA allowed (Normal Operations) 1 -- Reset, Not EEH stopped, MMIO load/store disabled, DMA disabled 2 -- Not reset, EEH stopped, MMIO load/store disabled, DMA disabled (Slot Frozen) An EEH error places the slot in state 2 (Frozen) and the adapter driver is notified that an EEH error was detected. If the adapter driver returns PCI_ERS_RESULT_NEED_RESET, the EEH driver calls eeh_reset_device() to place the slot into state 1 (Reset) and eeh_reset_device completes by placing the slot into State 0 (Normal Operations). Upon return from eeh_reset_device(), the EEH driver calls eeh_report_reset, which then calls the adapter's slot_reset callback. At the time the adapter's slot_reset callback is called, the true state of the hardware is Normal Operations and should be accurately reflected by setting dev->error_state to pci_channel_io_normal. The current implementation of EEH driver does not do so and requires this change to correct this deficiency. Signed-off-by: NMike Mason <mmlnx@us.ibm.com> Acked-by: NLinas Vepstas <linasvepstas@gmail.com> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Hugh Dickins 提交于
Now that shmem's divisions by zero and SHMEM_MAX_BYTES are fixed, let powerpc 256kB pages coexist with CONFIG_SHMEM again. Signed-off-by: NHugh Dickins <hugh@veritas.com> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Hugh Dickins 提交于
Revert part of af5c820a ("x86: cpumask: use work_on_cpu in arch/x86/kernel/microcode_core.c") That change is causing only one Intel CPU's microcode to be updated e.g. microcode: CPU3 updated from revision 0x9 to 0x17, date = 2005-04-22 where before it announced that also for CPU0 and CPU1 and CPU2. We cannot use work_on_cpu() in the CONFIG_MICROCODE_OLD_INTERFACE code, because Intel's request_microcode_user() involves a copy_from_user() from /sbin/microcode_ctl, which therefore needs to be on that CPU at the time. Signed-off-by: NHugh Dickins <hugh@veritas.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 14 4月, 2009 2 次提交
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由 Tony Breeds 提交于
In commit 51dcdfec ("parport: Use the PCI IRQ if offered") parport_pc_probe_port() gained an irqflags arg. This isn't being supplied on powerpc. This patch make powerpc fallback to the old behaviour, that is using "0" for irqflags. Fixes build failure: In file included from drivers/parport/parport_pc.c:68: arch/powerpc/include/asm/parport.h: In function 'parport_pc_find_nonpci_ports': arch/powerpc/include/asm/parport.h:32: error: too few arguments to function 'parport_pc_probe_port' arch/powerpc/include/asm/parport.h:32: error: too few arguments to function 'parport_pc_probe_port' arch/powerpc/include/asm/parport.h:32: error: too few arguments to function 'parport_pc_probe_port' make[3]: *** [drivers/parport/parport_pc.o] Error 1 Signed-off-by: NTony Breeds <tony@bakeyournoodle.com> Signed-off-by: NAlan Cox <alan@linux.intel.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Alan Cox 提交于
These got overlooked first time around. Signed-off-by: NAlan Cox <alan@linux.intel.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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