Move common nodes between GXBB and GXL in to the common GX dtsi.
Leave the clock attributes in the GXBB dtsi for now.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add binding and basic support for the SD/eMMC controller on Amlogic
S905/GXBB devices.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
[narmstrong: added nodes for GX, enabled SDIO on P20x]
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

In order to remove the boot warning :
[    2.290933] Unable to detect cache hierarchy from DT for CPU 0
And add missing L2 cache hierarchy information, add a simple l2 cache node
and reference it from the A53 cpu nodes.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Move all non-gxbb specific nodes to a common GX dtsi.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>