The commit 318c3e15
added some "fck" clock alias to timer devices that are
not needed anymore since hwmod framework will create
them automatically.

A warning was added to highlight and thus fix the redundancy.

[    0.616424]  omap_timer.1: alias fck already exists
[    0.621948]  omap_timer.2: alias fck already exists
[    0.627380]  omap_timer.3: alias fck already exists
[    0.632781]  omap_timer.4: alias fck already exists
[    0.638214]  omap_timer.5: alias fck already exists
[    0.643615]  omap_timer.6: alias fck already exists
[    0.649078]  omap_timer.7: alias fck already exists
[    0.654479]  omap_timer.8: alias fck already exists
[    0.659881]  omap_timer.9: alias fck already exists
[    0.665283]  omap_timer.10: alias fck already exists
[    0.670776]  omap_timer.11: alias fck already exists

Remove all the clkdev entries for timer fck alias.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can be
retrieved by doing a clk_get with the corresponding device pointers or
device names.
Reviewed-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NTarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: NThara Gopinath <thara@ti.com>
Acked-by: NCousson, Benoit <b-cousson@ti.com>
[tony@atomide.com: fixed typo in email address]
Signed-off-by: NTony Lindgren <tony@atomide.com>

The OMAP3505/AM3505 appears to be based on the same silicon as the
OMAP3517/AM3517, with some features disabled via eFuse bits.  Follow
the same practice as OMAP3430 and identify these devices internally as
part of the OMAP3517/AM3517 family.

The OMAP3503/3515/3525/3530 chips appear to be based on the same silicon
as the OMAP3430, with some features disabled via eFuse bits.  Identify
these devices internally as part of the OMAP3430 family.

Remove the old OMAP35XX_CLASS, which actually covered two very different
chip families.  The OMAP3503/3515/3525/3530 chips will now be covered by
OMAP343X_CLASS, since the silicon appears to be identical.  For the
OMAP3517/AM3517 family, create a new class, OMAP3517_CLASS.

Thanks to Tony Lindgren <tony@atomide.com> for some help with the second
revision of this patch.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Sanjeev Premi <premi@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Tested-by: NIgor Grinberg <grinberg@compulab.co.il>
Tested-by: NAbhilash Koyamangalath <abhilash.kv@ti.com>

The oscillator that supplies GPT12_FCLK and WDT1_FCLK exists in the
WKUP powerdomain[1].  This resolves at least one boot-time warning:

omap_hwmod: gpt12_fck: missing clockdomain for gpt12_fck.

1. _OMAP34xx Multimedia High Security (HS) Device Silicon Revision 3.1.x
   Security Addendum Version K (SWPU119K)_  Figure 3-29.  August 2010.

Extend the existing function to create clkdev for every optional
clocks to add a well one "fck" alias for the main_clk of the
omap_hwmod.
It will allow to remove these static clkdev entries from the
clockXXX_data.c file.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Todd Poynor <toddpoynor@google.com>
[paul@pwsan.com: remove all of the "fck" role clkdev aliases from the
 clock data files; fixed error message]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Currently, clock database has <dev, clock-name> tuples for DSS2. Because of
this, the clock names are different across different OMAP platforms.

This patch aligns the DSS2 clock names and roles across OMAP 2420, 2430, 3xxx,
44xx platforms in the clock databases, hwmod databases for opt-clocks, and DSS
clock handling.

This ensures that clk_get/put/enable/disable APIs in DSS can use uniform role
names.
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Acked-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

All clock management is moved to dss platform driver. clk_get/put APIs use
dss device instead of core platform device.

Hwmod adaptation design requires each of the DSS HW IP to be a platform driver.
So the device name is changed from omapdss to omapdss_dss in 2420, 2430,
3xxx clock database files. Now the core driver "omapdss" only takes care
of panel registration with the custom bus.
core driver also uses the clk_enable() / clk_disable() APIs exposed by DSS for
clock management.
DSS driver would do clock management of clocks needed by DISPC, RFBI, DSI, VENC

TODO:  The clock content would be adapted to omap_hwmod in a seperate series.
Signed-off-by: NSenthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Remove the DPLL rate tolerance code that is called during rate
rounding.  As far as I know, this code is never used, since it's been
more important for callers of the DPLL round_rate()/set_rate()
functions to obtain an exact rate than it is to save a relatively
small amount of power.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Mark each interface clock with a corresponding CM_AUTOIDLE bit with
a clkops that has the allow_idle/deny_idle function pointers populated.
This allows the OMAP clock framework to enable and disable autoidle for
these clocks.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

Modifying the device & driver name from "mmci-omap-hs" to
"omap_hsmmc".
Signed-off-by: NKishore Kadiyala <kishore.kadiyala@ti.com>
Acked-by: Benoit Cousson<b-cousson@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The devices of clocks are set to usbhs, so that
only usbhs common driver can invoke these clocks.
The dummy per port clocks are added to omap3
clock data base. This helps to invoke common
clock get APIs for omap3 and omap4.
Signed-off-by: NKeshava Munegowda <keshava_mgowda@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Disable autoidle on all clocks during clock framework initialization.
(If CONFIG_PM is set, autoidle is re-enabled for all clocks later in
the boot process.)

The principle behind this patch, and some similar patches, is that the
kernel should start with all power management features disabled.
Later in the boot process, the PM code, if compiled in with CONFIG_PM,
enables or re-enables power management features.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>

All OMAP3/4 dpll's support hardware level autogating.
Populate allow_idle/deny_idle function pointers for all
DPLL's in clkops.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

DPLL1 on omap3 is very similar to the rest of
the non-core dpll's.
Hence populate clkops_omap3_noncore_dpll_ops
as the clkops for it, instead of the
currently populated clkops_null.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

This patch updates the common machine specific source files with support for
TI816X.
Signed-off-by: NHemant Pedanekar <hemantp@ti.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

At latest mainline commit 0c21e3aa,  omap2plus build is broken. This
patch is trivial fix for the missed usb clock node for CK_3430ES2PLUS
flag update.

 CHK     include/generated/compile.h
  CC      arch/arm/mach-omap2/clock3xxx_data.o
arch/arm/mach-omap2/clock3xxx_data.c:3289: error: 'CK_3430ES2' undeclared
here (not in a function)
make[1]: *** [arch/arm/mach-omap2/clock3xxx_data.o] Error 1
make: *** [arch/arm/mach-omap2] Error 2
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: NAnand Gadiyar <gadiyar@ti.com>
Acked-by: NPaul Walmsley <paul@pwsan.com>
[tony@atomide.com: updated mask to include CK_36XX]
Signed-off-by: NTony Lindgren <tony@atomide.com>

J-Type DPLLs have additional configuration parameters that need to
be programmed when setting the multipler and divider for the DPLL.
These parameters being the sigma delta divider (SD_DIV) for the DPLL
and the digital controlled oscillator (DCO) to be used by the DPLL.

The current code is implemented specifically to configure the
OMAP3630 PER J-Type DPLL. The OMAP4430 USB DPLL is also a J-Type DPLL
and so this code needs to be updated to work for both OMAP3 and OMAP4
devices and any other future devices that have J-TYPE DPLLs.

For the OMAP3630 PER DPLL both the SD_DIV and DCO paramenters are
used but for the OMAP4430 USB DPLL only the SD_DIV field is used.
The current implementation will only program the SD_DIV and DCO
fields if the DPLL has both and hence this does not work for
OMAP4430.

In order to make the code more generic add two new fields to the
dpll_data structure for the SD_DIV field and DCO field bit-masks
and only program these fields if the masks are defined for a specific
DPLL. This simplifies the code and allows us to remove the flag
DPLL_NO_DCO_SEL.

Tested on OMAP36xx Zoom3 and OMAP4 Blaze.
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: removed explicit inlining and added '_' prefix on lookup_*()
 functions; added testing info to commit message; added 35xx comments back in]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Update clock3xxx_data for mcspi1-4 with appropriate clock domain name.
Signed-off-by: NCharulatha V <charu@ti.com>
Signed-off-by: NGovindraj.R <govindraj.raja@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Clarify the usage of the struct omap_clk.cpu flags (e.g., CK_*) to use
bits only for individual SoC variants (e.g., CK_3430ES1, CK_3505,
etc.).  Superset flags, such as CK_3XXX or CK_AM35XX, are now defined
as disjunctions of individual SoC variant flags.  This simplifies the
definition and use of these flags.  struct omap_clk record definitions
can now simply specify the bitmask of actual SoCs that the records are
valid for.  The clock init code can simply set a single CPU type mask
bit for the SoC that is currently in use, and test against that,
rather than needing to set some combination of flags.

Similarly, clarify the use of struct clksel_rate.flags.  The bit
allocated for RATE_IN_3XXX has been reassigned, and RATE_IN_3XXX has
been defined as a disjunction of the 34xx and 36xx rate flags.  The
advantages are the same as the above.

Clarify the usage of struct omap_clk.cpu flags such as CK_34XX to only
apply to the SoCs that they name, e.g., OMAP34xx chips.  The previous
practice caused significantly different SoCs, such as OMAP36xx, to be
included in CK_34XX.  In my opinion, this is much more intuitive.

Similarly, clarify the use of struct clksel_rate.flags, such that
RATE_IN_3430ES2PLUS now only applies to 34xx chips with ES level >= 2
- it does not apply to OMAP36xx.

...

At some point, it probably makes sense to collapse the CK_* and
RATE_IN_* flags together into a single bitfield, and possibly use the
existing CHIP_IS_OMAP* flags for platform detection.

...

This all seems to work fine on OMAP34xx and OMAP36xx Beagle.  Not sure
if it works on Sitara or the TI816X, unfortunately I don't have any
here to test with.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The smartreflex modules belong to an ALWON_FCLK clock domain that
does not have any SW control. The gating of that interface clock
is triggered by a transition of the WKUP clock domain to idle.

Attach both smartreflex instances on OMAP3 to the WKUP clock domain.

The missing clock domain field in srX_fck clock nodes was reported by
Kevin during the discussion about smartreflex on OMAP3:
https://patchwork.kernel.org/patch/199342/Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>

In preparation for adding OMAP4-specific PRCM accessor/mutator
functions, split the existing OMAP2/3 PRCM code into OMAP2/3-specific
files.  Most of what was in mach-omap2/{cm,prm}.{c,h} has now been
moved into mach-omap2/{cm,prm}2xxx_3xxx.{c,h}, since it was
OMAP2xxx/3xxx-specific.

This process also requires the #includes in each of these files to be
changed to reference the new file name.  As part of doing so, add some
comments into plat-omap/sram.c and plat-omap/mcbsp.c, which use
"sideways includes", to indicate that these users of the PRM/CM includes
should not be doing so.

Thanks to Felipe Contreras <felipe.contreras@gmail.com> for comments on this
patch.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Cc: Liam Girdwood <lrg@slimlogic.co.uk>
Cc: Omar Ramirez Luna <omar.ramirez@ti.com>
Acked-by: NOmar Ramirez Luna <omar.ramirez@ti.com>
Cc: Felipe Contreras <felipe.contreras@gmail.com>
Acked-by: NFelipe Contreras <felipe.contreras@gmail.com>
Cc: Greg Kroah-Hartman <greg@kroah.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Reviewed-by: NKevin Hilman <khilman@deeprootsystems.com>
Tested-by: NKevin Hilman <khilman@deeprootsystems.com>
Tested-by: NRajendra Nayak <rnayak@ti.com>
Tested-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

The convention for omap device naming is omap_XXX.

Rename the device and driver name in order to stick
to this naming convention.

Change device name in clock nodes as well.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Ben Dooks <ben-i2c@fluff.org>
Acked-by: NPaul Walmsley <paul@pwsan.com>
Acked-by: NBen Dooks <ben-linux@fluff.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

musb core doesn't need to know about platform
specific details. So start moving clock
handling to platform glue layer and make
musb core agnostic about that.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

change all ocurrences of musb_hdrc to musb-hdrc.

We will call glue layer drivers musb-<glue layer>,
so in order to keep things somewhat standard, let's
change the underscore into a dash.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Add clkdev aliases for the USBHOST and USBTLL clocks on OMAP3 and
OMAP4, so that the driver can refer to the clocks using a common alias.

This will disappear when the driver is converted to use the hwmod
database, but until then this patch is needed.
Signed-off-by: NAnand Gadiyar <gadiyar@ti.com>
Acked-by: NPaul Walmsley <paul@pwsan.com>
Acked-by: NTony Lindgren <tony@atomide.com>

Only OMAP2+ platforms have the System Control Module (SCM) IP block.
In the past, we've kept the SCM header file in plat-omap.  This has
led to abuse - device drivers including it; includes being added that
create implicit dependencies on OMAP2+ builds; etc.

In response, move the SCM headers into mach-omap2/.

As part of this, remove the direct SCM access from the OMAP UDC
driver.  It was clearly broken.  The UDC code needs an indepth review for
use on OMAP2+ chips.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Cory Maccarrone <darkstar6262@gmail.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>

The OMAP3 clock tree already contains the infrastructure to support
clock framework-based McBSP functional clock source switching.  But it
did not contain the clkdev aliases for the McBSP code to refer to the
parent clocks in an SoC integration-neutral way.  So, add the clkdev
aliases for the parent clocks.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

This is only valid for omap 36xx family of chips.
Signed-off-by: NSergio Aguirre <saaguirre@ti.com>
Signed-off-by: NGovindraj.R <govindraj.raja@ti.com>
Acked-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Updates to enable omap aes
Signed-off-by: NDmitry Kasatkin <dmitry.kasatkin@nokia.com>
[tony@atomide.com: updated to use CONFIG_ARCH_OMAP2/3 instead of old 24XX/34XX]
Signed-off-by: NTony Lindgren <tony@atomide.com>

Signed-off-by: NDmitry Kasatkin <dmitry.kasatkin@nokia.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

cpu_is_omap3517() and cpu_is_omap3505() are the subgroups of cpu_is_omap34xx(),
so we should check cpu_is_omap3517() and cpu_is_omap3505() first, then check
cpu_is_omap34xx().

Otherwise, All AM35XX (Sitara) clocks do not get registered and device drivers
(ti_hecc, etc...) that depend on those clocks are failing to get the clock and
end up with non working device.
Signed-off-by: NStanley.Miao <stanley.miao@windriver.com>
Tested-by: NIgor Grinberg <grinberg@compulab.co.il>
Signed-off-by: NTony Lindgren <tony@atomide.com>

We need to wait on the IDLEST bit after the clocks are enabled
before attempting to access any register.

Currently, the USBTLL i-clock ops uses the clkops_omap2_dflt_wait,
while the USBTLL f-clock ops uses clkops_omap2_dflt. If the
i-clock is enabled first, the clkops_omap2_dflt_wait is
short-circuited as the companion f-clock is not enabled.
This can cause a data abort if the IDLEST has not transitioned,
and we try to access a USBTLL register.

Since the USBTLL i-clock and f-clock could be enabled in any order,
this is a bug. Fix it by changing the clkops for the f-clock.
Signed-off-by: NAnand Gadiyar <gadiyar@ti.com>
Acked-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add a dummy clk definition for the APB pclk signal on all platforms
using the AMBA bus infrastructure.  This ensures that these platforms
continue to work when the core amba bus code controls the APB pclk.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add clock framework support for changing the rate of sys_clkout2.
Signed-off-by: NLaine Walker-Avina <lwalkera@ieee.org>
[paul@pwsan.com: added commit message, added .round_rate pointer]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Commit 678bc9a2 split dpll4_m2_ck,
creating a 34xx and a 36xx variant, to handle the additional 16
divider steps provided on the 36xx.  This in turn required dynamic
rewriting of the clock tree during initialization, which is
undesirable.  All this seems to be unnecessary, though, since the
additional 16 divider steps can simply be marked with RATE_IN_36XX.
This patch does so and re-merges the affected structures.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Vishwanath Sripathy <vishwanath.bs@ti.com>

Rename the RATE_IN_343X clksel_rate.rate flag to be RATE_IN_3XXX, to reflect
that these rates are valid on all OMAP3 platforms, not just 343X.

Also rename the RATE_IN_OMAP3430ES2 clksel_rate.rate flag to be
RATE_IN_OMAP3430ES2PLUS, to reflect that these flags are valid on all
OMAP3 platforms after 3430ES2.

This patch should not result in any functional changes.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Ranjith Lohithakshan <ranjithl@ti.com>

The DEFAULT_RATE clksel_rate flag is essentially useless.  It was set
on some of the lowest divisors, which, when switching to a much
higher-rate parent, could have potentially resulted in rates that
exceeded the hardware specifications for downstream clocks in the
window between the clk_set_parent(), and a subsequent clk_set_rate().
It seems much safer to just remove the flag and always use the highest
available divisor (resulting in the lowest possible rate) after the
switch, and this patch does so.

Ideally, it would be best to first attempt to switch to a divisor that
matches the clock's rate with the previous parent, if at all possible.
But that is a project for some other day or some other person.  The
parent changing code is rarely used.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The emac driver currently uses Davinci clock names for the module and phy
clocks. Updated the omap3xxx_clks table to match the names
used by the Davinci emac driver.

Note that eventually the EMAC clocks should be renamed to be generic.
Signed-off-by: NSriramakrishnan <srk@ti.com>
Acked-by: NPaul Walmsley <paul@pwsan.com>
[tony@atomide.com: updated patch description to match the patch]
Signed-off-by: NTony Lindgren <tony@atomide.com>

- registration with multi OMAP kernels support
- clocks
Signed-off-by: NDmitry Kasatkin <dmitry.kasatkin@nokia.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The enable bit for dpll4_m4x2 clock should be OMAP3430_PWRDN_DSS1_SHIFT.
The code erroneously uses OMAP3430_PWRDN_CAM_SHIFT which is meant for
dpll4_m5x2 clock.

This came into notice during a recent review of the clock tree.
Signed-off-by: NRanjith Lohithakshan <ranjithl@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>