1. 19 12月, 2013 1 次提交
  2. 16 12月, 2013 12 次提交
  3. 02 12月, 2013 1 次提交
  4. 25 11月, 2013 1 次提交
  5. 20 11月, 2013 1 次提交
    • H
      s390/mm: optimize copy_page · dba6bb60
      Heiko Carstens 提交于
      Always use the mvcl instruction to copy a page instead of mvpg or a
      couple of mvc instructions.
      Copying a huge page is 25% faster this way. Also bypass caches when
      copying pages since only parts of a page will be used afterwards.
      Especially when copying a huge page this would kick everything out
      of the L1 and L2 data caches on a zEC12 machine.
      Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
      dba6bb60
  6. 15 11月, 2013 6 次提交
  7. 14 11月, 2013 2 次提交
  8. 04 11月, 2013 1 次提交
    • M
      s390/mm,tlb: correct tlb flush on page table upgrade · 10607864
      Martin Schwidefsky 提交于
      The IDTE instruction used to flush TLB entries for a specific address
      space uses the address-space-control element (ASCE) to identify
      affected TLB entries. The upgrade of a page table adds a new top
      level page table which changes the ASCE. The TLB entries associated
      with the old ASCE need to be flushed and the ASCE for the address space
      needs to be replaced synchronously on all CPUs which currently use it.
      The concept of a lazy ASCE update with an exception handler is broken.
      Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      10607864
  9. 31 10月, 2013 2 次提交
  10. 24 10月, 2013 13 次提交
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