“3fcd16ede3dd71b269fed8ae213d18491b65f186”上不存在“paddle/fluid/platform/cudnn_desc_test.cc”
  1. 13 5月, 2008 1 次提交
    • V
      x86: remove 6 bank limitation in 64 bit MCE reporting code · 8edc5cc5
      Venki Pallipadi 提交于
      Eliminate the 6 bank restriction in 64 bit mce reporting code. This
      restriction is artificial (due to static creation of sysfs files) and 32
      bit code does not have any such restriction.
      
      This change helps in reporting the details of machine checks on a
      machine check exception with errors in bank 6 and above on CPUs that
      support those banks. Without the patch, machine check errors in those
      banks are not reported.
      
      We still have 128 (MCE_EXTENDED_BANK) bank restriction instead of max
      256 supported in hardware. That is not changed in the patch below as it
      will have some user level mcelog utility dependency, with bank 128 being
      used for thermal reporting currently.
      
      The patch below does not create sysfs control (bankNctl) for banks
      higher than 6 as well. That needs some pre-cleanup in /sysfs mce layout,
      removal of per cpu /sysfs entries for bankctl as they are really global
      system level control today. That change will follow. This basic change
      is critical to report the detailed errors on banks higher than 6.
      Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8edc5cc5
  2. 08 5月, 2008 1 次提交
    • T
      x86: cleanup PAT cpu validation · 8d4a4300
      Thomas Gleixner 提交于
      Move the scattered checks for PAT support to a single function. Its
      moved to addon_cpuid_features.c as this file is shared between 32 and
      64 bit.
      
      Remove the manipulation of the PAT feature bit and just disable PAT in
      the PAT layer, based on the PAT bit provided by the CPU and the
      current CPU version/model white list.
      
      Change the boot CPU check so it works on Voyager somewhere in the
      future as well :) Also panic, when a secondary has PAT disabled but
      the primary one has alrady switched to PAT. We have no way to undo
      that.
      
      The white list is kept for now to ensure that we can rely on known to
      work CPU types and concentrate on the software induced problems
      instead of fighthing CPU erratas and subtle wreckage caused by not yet
      verified CPUs. Once the PAT code has stabilized enough, we can remove
      the white list and open the can of worms.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8d4a4300
  3. 29 4月, 2008 4 次提交
  4. 26 4月, 2008 4 次提交
    • D
      x86: remove NexGen support · f7f17a67
      Dmitri Vorobiev 提交于
      It is claimed that NexGen CPUs were never shipped:
      
         http://lkml.org/lkml/2008/4/20/179
      
      Also, the kernel support for these chips has been broken for
      a long time, the code intended to support NexGen thereby being
      essentially dead.
      
      As an outcome of the discussion that can be found using the URL
      above, this patch removes the NexGen support altogether.
      
      The changes in this patch survived a defconfig build for i386, a
      couple of successful randconfig builds, as well as a runtime test,
      which consisted in booting a 32-bit x86 box up to the shell prompt.
      Signed-off-by: NDmitri Vorobiev <dmitri.vorobiev@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f7f17a67
    • D
      x86: remove unused function amd_init_cpu() · f3b14a32
      Dmitri Vorobiev 提交于
      There are no users for the function amd_init_cpu() defined in
      arch/x86/kernel/cpu/amd.c. This patch removes this routine.
      
      This patch was build-tested using defconfigs for i386 and x86_64,
      and a few randconfig instances. Runtime tests were performed by
      booting 32- and 64-bit x86 boxen up to the shell prompt.
      Signed-off-by: NDmitri Vorobiev <dmitri.vorobiev@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f3b14a32
    • J
      x86-64: extend MCE CPU quirk handling · 911f6a7b
      Jan Beulich 提交于
      At least on my Barcelona, I see MCE log entries after cold boot caused
      by BIOS not properly clearing the respective registers. Therefore, this
      patch extends the workaround to families 0x10 and 0x11 (the latter just
      for completeness, I have nothing to verify this against).
      At the same time, provide a way to make these entries visible via the
      'mce=bootlog' command line option even on these machines.
      Signed-off-by: NJan Beulich <jbeulich@novell.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      911f6a7b
    • J
      x86: fix watchdog ops for CoreDuo · 86d78f64
      Jan Beulich 提交于
      There apparently was an unnoticed conflict between an earlier patch to
      this file and mine (d1e08474), which
      I noticed only now. I suppose a change like the one below (untested) is
      needed; I didn't get any response on a confirmation request for this from
      the submitter of the first patch.
      
      The issue is the writing of the 'checkbit' member at the end of
      setup_intel_arch_watchdog(), which my patch made go to intel_arch_wd_ops
      rather than wd_ops.
      Signed-off-by: NJan Beulich <jbeulich@novell.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      86d78f64
  5. 20 4月, 2008 6 次提交
  6. 19 4月, 2008 1 次提交
  7. 17 4月, 2008 23 次提交