1. 13 5月, 2008 1 次提交
    • V
      x86: remove 6 bank limitation in 64 bit MCE reporting code · 8edc5cc5
      Venki Pallipadi 提交于
      Eliminate the 6 bank restriction in 64 bit mce reporting code. This
      restriction is artificial (due to static creation of sysfs files) and 32
      bit code does not have any such restriction.
      
      This change helps in reporting the details of machine checks on a
      machine check exception with errors in bank 6 and above on CPUs that
      support those banks. Without the patch, machine check errors in those
      banks are not reported.
      
      We still have 128 (MCE_EXTENDED_BANK) bank restriction instead of max
      256 supported in hardware. That is not changed in the patch below as it
      will have some user level mcelog utility dependency, with bank 128 being
      used for thermal reporting currently.
      
      The patch below does not create sysfs control (bankNctl) for banks
      higher than 6 as well. That needs some pre-cleanup in /sysfs mce layout,
      removal of per cpu /sysfs entries for bankctl as they are really global
      system level control today. That change will follow. This basic change
      is critical to report the detailed errors on banks higher than 6.
      Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8edc5cc5
  2. 11 5月, 2008 3 次提交
  3. 08 5月, 2008 2 次提交
    • T
      x86: cleanup PAT cpu validation · 8d4a4300
      Thomas Gleixner 提交于
      Move the scattered checks for PAT support to a single function. Its
      moved to addon_cpuid_features.c as this file is shared between 32 and
      64 bit.
      
      Remove the manipulation of the PAT feature bit and just disable PAT in
      the PAT layer, based on the PAT bit provided by the CPU and the
      current CPU version/model white list.
      
      Change the boot CPU check so it works on Voyager somewhere in the
      future as well :) Also panic, when a secondary has PAT disabled but
      the primary one has alrady switched to PAT. We have no way to undo
      that.
      
      The white list is kept for now to ensure that we can rely on known to
      work CPU types and concentrate on the software induced problems
      instead of fighthing CPU erratas and subtle wreckage caused by not yet
      verified CPUs. Once the PAT code has stabilized enough, we can remove
      the white list and open the can of worms.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8d4a4300
    • A
      x86: GEODE: cache results from geode_has_vsa2() and uninline · 547acec7
      Andres Salomon 提交于
      This moves geode_has_vsa2 into a .c file, caches the result we get from
      the VSA virtual registers, and causes the function to no longer be inline.
      
      [akpm@linux-foundation.org: cleanup]
      Signed-off-by: NAndres Salomon <dilinger@debian.org>
      Cc: Jordan Crouse <jordan.crouse@amd.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      547acec7
  4. 07 5月, 2008 1 次提交
  5. 05 5月, 2008 6 次提交
  6. 04 5月, 2008 2 次提交
  7. 01 5月, 2008 6 次提交
  8. 30 4月, 2008 1 次提交
  9. 29 4月, 2008 13 次提交
  10. 28 4月, 2008 1 次提交
  11. 27 4月, 2008 4 次提交