1. 13 2月, 2012 1 次提交
    • D
      drm/modes: do not enforce an odd vtotal for interlaced modes · 8bf42225
      Daniel Vetter 提交于
      CEA actually specifies an interlaced mode with even vtotal and
      supplies a diagram showing how this is supposed to work.
      
      Note that interlaced modes with an even vtotal seem to be a fairly
      recent invention. All modelines lore I could dig up with googling says
      that vtotal for interlaced modes _needs_ to be odd. But the even
      modelines in CEA are not a spec-bug, there's a figure in CEA-861-E
      called "Figure 5 Special Interlaced Video Format Timing (Even Vtotal)"
      that explains how it's supposed to work. Furthermore intel Bspec
      explicitly mentions that both odd and even interlaced vtotal are
      supported (VTOTAL register in the south display engine of PCH split
      chips).
      Acked-by: NAdam Jackson <ajax@redhat.com>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      8bf42225
  2. 09 2月, 2012 3 次提交
  3. 07 2月, 2012 1 次提交
    • D
      Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next · 198ceac0
      Dave Airlie 提交于
      * 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel:
        drm/i915: add a LLC feature flag in device description
        drm/i915: kill i915_mem.c
        drm/i915: Use kcalloc instead of kzalloc to allocate array
        drm/i915/dp: Check for AUXCH error before checking for success
        drm/i915/dp: Use auxch precharge value of 5 everywhere
        drm/i915/dp: Tweak auxch clock divider for PCH
        drm/i915: Remove a comment about PCH from the non-PCH path
        drm/i915: Fix assert_pch_hdmi_disabled to mention HDMI (not DP)
        drm/i915: Implement plane-disabled assertion for PCH too
        drivers: i915: Fix BLC PWM register setup
        drm/i915: Check that plane/pipe is disabled before removing the fb
        drm/i915: fix typo in function name
        drm/i915: split out pll divider code
        drm/i915: split 9xx refclk & sdvo tv code out
        agp/intel: Add pci id for hostbridge from has/qemu
        drm/i915: there is no pipe CxSR on ironlake
        drm/i915: Only look for matching clocks for LVDS downclock
        drm/i915: Silence _DSM errors
      198ceac0
  4. 03 2月, 2012 32 次提交
  5. 02 2月, 2012 3 次提交