1. 13 2月, 2017 2 次提交
    • H
      mfd: axp20x: Add missing axp288 irqs · 8b44e678
      Hans de Goede 提交于
      The axp288 has the following irqs 2 times: VBUS_FALL, VBUS_RISE,
      VBUS_OV. On boot / reset the enable flags for both the normal and alt
      version of these irqs is set.
      
      Since we were only listing the normal version in the axp288 regmap_irq
      struct, we were never disabling the alt versions of these irqs.
      
      Add the alt versions to the axp288 regmap_irq struct, so that these
      get properly disabled.
      
      Together with the other axp288 fixes in this series, this fixes the axp288
      irq contineously triggering.
      Signed-off-by: NHans de Goede <hdegoede@redhat.com>
      Acked-by: NChen-Yu Tsai <wens@csie.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      8b44e678
    • H
      mfd: axp20x: Use IRQF_TRIGGER_LOW on the axp288 · 0a5454c9
      Hans de Goede 提交于
      The interrupt line of the entire family of axp2xx pmics is active-low,
      for devicetree enumerated irqs, this is dealt with in the devicetree.
      
      ACPI irq resources have a flag field for this too, I tried using this
      on my CUBE iwork8 Air tablet, but it does not contain the right data.
      
      The dstd shows the irq listed as either ActiveLow or ActiveHigh,
      depending on the OSID variable, which seems to be set by the
      "OS IMAGE ID" in the BIOS/EFI setup screen.
      
      Since the acpi-resource info is no good, simply pass in IRQF_TRIGGER_LOW
      on the axp288.
      
      Together with the other axp288 fixes in this series, this fixes the axp288
      irq contineously triggering.
      Signed-off-by: NHans de Goede <hdegoede@redhat.com>
      Acked-by: NChen-Yu Tsai <wens@csie.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      0a5454c9
  2. 29 11月, 2016 1 次提交
    • C
      mfd: axp20x: Add address extension registers for AXP806 regmap · 34d9030b
      Chen-Yu Tsai 提交于
      The AXP806 supports either master/standalone or slave mode.
      Slave mode allows sharing the serial bus, even with multiple
      AXP806 which all have the same hardware address.
      
      This is done with extra "serial interface address extension",
      or AXP806_BUS_ADDR_EXT, and "register address extension", or
      AXP806_REG_ADDR_EXT, registers. The former is read-only, with
      1 bit customizable at the factory, and 1 bit depending on the
      state of an external pin. The latter is writable. Only when
      the these device addressing bits (in the upper 4 bits of the
      registers) match, will the device respond to operations on
      its other registers.
      
      Add these 2 registers to the regmap so we can access them.
      Signed-off-by: NChen-Yu Tsai <wens@csie.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      34d9030b
  3. 21 11月, 2016 1 次提交
  4. 04 10月, 2016 1 次提交
  5. 13 9月, 2016 1 次提交
    • C
      mfd: axp20x: Add support for AXP806 PMIC · 8824ee85
      Chen-Yu Tsai 提交于
      The X-Powers AXP806 is a new PMIC that is paired with Allwinner's A80
      SoC, along with a master AXP809 PMIC.
      
      This PMIC has a new register layout, and supports some functions not
      seen in other X-Powers PMICs, such as master-slave mode, or having
      multiple AXP806 PMICs on the same bus with address space extension,
      or supporting both I2C and RSB mode. I2C has not been tested.
      
      This patch adds support for the interrupts of the PMIC. A regulator
      sub-device is enabled, but actual regulator support will come in a
      later patch.
      Signed-off-by: NChen-Yu Tsai <wens@csie.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      8824ee85
  6. 29 6月, 2016 3 次提交
  7. 09 5月, 2016 1 次提交
  8. 19 4月, 2016 1 次提交
  9. 12 2月, 2016 6 次提交
  10. 31 10月, 2015 1 次提交
  11. 12 8月, 2015 2 次提交
  12. 11 8月, 2015 2 次提交
  13. 13 5月, 2015 2 次提交
    • C
      mfd: axp20x: Enable AXP22X regulators · 6d4fa89d
      Chen-Yu Tsai 提交于
      Now that the axp20x-regulators driver supports different variants of the
      AXP family, we can enable regulator support for AXP22X without the risk
      of incorrectly configuring regulators.
      Signed-off-by: NChen-Yu Tsai <wens@csie.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      6d4fa89d
    • B
      mfd: axp20x: Add AXP22x PMIC support · f05be589
      Boris BREZILLON 提交于
      Add support for the AXP22x PMIC devices to the existing AXP20x driver.
      This includes the AXP221 and AXP223, which are identical except for
      the external data bus. Only AXP221 is added for now. AXP223 will be
      added after it's Reduced Serial Bus (RSB) interface is supported.
      
      AXP22x defines a new set of registers, power supplies and regulators,
      but most of the API is similar to the AXP20x ones.
      
      A new irq chip definition is used, even though the available interrupts
      on AXP22x is a subset of those on AXP20x. This is done so the interrupt
      numbers match those on the datasheet.
      
      This patch only enables the interrupts, system power-off function, and PEK
      sub-device. The regulator driver must first support different variants
      before we enable it from the mfd driver.
      Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
      [wens@csie.org: fix interrupts and move regulators to separate patch]
      Signed-off-by: NChen-Yu Tsai <wens@csie.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      f05be589
  14. 09 4月, 2015 1 次提交
  15. 30 3月, 2015 1 次提交
  16. 08 3月, 2015 1 次提交
  17. 04 3月, 2015 1 次提交
  18. 27 11月, 2014 1 次提交
  19. 26 11月, 2014 1 次提交
  20. 18 11月, 2014 1 次提交
    • J
      mfd/axp20x: avoid irq numbering collision · ff3bbc5c
      Jacob Pan 提交于
      IRQ numbers in axp20x devices are defined with high-order bit first
      in each IRQ enable/status registers. On Intel platforms it is more
      common to number IRQs with least significant bit first. Therefore,
      sharing IRQ# between the two is very difficult. Since AXP288 is a
      customized PMIC for Intel platform and the amount of shared IRQs are
      very small, we use separate IRQ numbering. This also fixes collision
      and a duplicate in WBTO interrupt.
      
      e.g. For the 16 interrupts controlled in IRQ enabled registers 1 & 2,
      on axp20x for ARM, the PMIC local IRQ numbers and register bits are
      mapped as:
      IRQ#:  0  1  2  3  4  5  6  7      8  9 10 11 12 13 14 15
      ---------------------------------------------------------
      ARM:   7  6  5  4  3  2  1  0      7  6  5  4  3  2  1  0
      Intel: 0  1  2  3  4  5  6  7      0  1  2  3  4  5  6  7
      Signed-off-by: NTodd Brandt <todd.e.brandt@linux.intel.com>
      Signed-off-by: NJacob Pan <jacob.jun.pan@linux.intel.com>
      Acked-by: NJonathan Cameron <jic23@kernel.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      ff3bbc5c
  21. 07 10月, 2014 1 次提交
  22. 26 9月, 2014 1 次提交
  23. 03 6月, 2014 1 次提交