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  1. 20 6月, 2006 2 次提交
  3. 18 6月, 2006 1 次提交
  5. 09 6月, 2006 1 次提交
  7. 06 6月, 2006 1 次提交
  9. 18 5月, 2006 1 次提交
  11. 06 5月, 2006 1 次提交
  13. 19 4月, 2006 1 次提交
  15. 03 4月, 2006 1 次提交
  17. 01 4月, 2006 3 次提交
  19. 29 3月, 2006 1 次提交
  21. 28 3月, 2006 1 次提交
  23. 27 3月, 2006 1 次提交
  25. 24 3月, 2006 1 次提交
  27. 22 3月, 2006 3 次提交
  29. 02 2月, 2006 1 次提交
  31. 14 1月, 2006 1 次提交
  33. 13 1月, 2006 1 次提交
  35. 09 1月, 2006 1 次提交
    • R
      [PATCH] IRQ type flags · 9ded96f2
      由 Russell King 提交于 
      Some ARM platforms have the ability to program the interrupt controller to
detect various interrupt edges and/or levels.  For some platforms, this is
critical to setup correctly, particularly those which the setting is dependent
on the device.

Currently, ARM drivers do (eg) the following:

	err = request_irq(irq, ...);

	set_irq_type(irq, IRQT_RISING);

However, if the interrupt has previously been programmed to be level sensitive
(for whatever reason) then this will cause an interrupt storm.

Hence, if we combine set_irq_type() with request_irq(), we can then safely set
the type prior to unmasking the interrupt.  The unfortunate problem is that in
order to support this, these flags need to be visible outside of the ARM
architecture - drivers such as smc91x need these flags and they're
cross-architecture.

Finally, the SA_TRIGGER_* flag passed to request_irq() should reflect the
property that the device would like.  The IRQ controller code should do its
best to select the most appropriate supported mode.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      9ded96f2
  37. 07 1月, 2006 1 次提交
  39. 06 1月, 2006 8 次提交
  41. 05 1月, 2006 1 次提交
  43. 13 12月, 2005 1 次提交
    • L
      [ARM] 3201/1: PXA27x: Prevent hangup during resume due to inadvertedly... · 1ee9530a
      由 Lothar Wassmann 提交于 
      [ARM] 3201/1: PXA27x: Prevent hangup during resume due to inadvertedly enabling MBREQ (replaces: 3198/1)

Patch from Lothar Wassmann

The patch makes sure, that the ouptut functions of pins are restored
before restoring the Alternat Function settings, preventing pins from
being intermediately configured for undefined or unwanted alternate
functions.

Here is the original comment:
I've got a PXA270 system that uses GPIO80 as nCS4. This system did
hang on resume. Digging into the problem I found that the processor
stalled immediately when restoring the GAFR2_U register which restored
the alternate function for GPIO80. Since the GPDR registers were
restored after the GAFR registers, the offending GPIO was configured
as input at this point.
Thus the alternate function that was in effect after restoring the
GAFR was in fact the input function "MBREQ" instead of the output
function "nCS4". The "PXA27x Processor Family Developer's Manual"
(Footnote in Table 6-1 on page 6-3) states that:
"The MBREQ alternate function must not be enabled until the PSSR[RDH]
bit field is cleared. For more details, see Table 3-15, "PSSR Bit
Definitions" on page 3-71."

There is another note in the Developer's Manual (chapter 24.4.2
"GPIO operation as Alternate Function" on page 24-4)
stating that:
"Configuring a GPIO for an alternate function that is not defined for
it causes unpredictable results."

Since some GPIOs have no input function defined, and to prevent
inadvertedly programming the MBREQ function on some pin, the GAFR
registers should be restored after the GPDR registers have been
restored.

Additional provisions have to be made when the MBREQ function is
actually required. The corresponding GAFR bits should not be restored
with the regular GAFR restore, but must be set only after the PSSR
bits have been cleared.
Signed-off-by: NLothar Wassmann <LW@KARO-electronics.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      1ee9530a
  45. 01 12月, 2005 1 次提交
  47. 29 11月, 2005 1 次提交
  49. 21 11月, 2005 1 次提交
  51. 16 11月, 2005 1 次提交
  53. 13 11月, 2005 2 次提交