As Google/Intel will fix the BIOS/Coreboot issues with hardcoding
virtual interrupt numbers for keyboard/touchpad/touchscreen controllers
in ACPI tables, they will also update BOARD version number from 1.0
to 1.1. Let's limit the DMI quirks that try to preserve virtual IRQ
numbers on Strago boards to those that still carry older BIOSes.

Note that ideally not BOARD but BIOS version should have been updated.
However the BIOS version used by Chrome devices has format of
Google_BUILD.BRANCH.PATCH which is not well suited for DMI matching as
we do not have "less than" match mode for DMI data.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=197953Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The device node iterators perform an of_node_get on each iteration, so a
jump out of the loop requires an of_node_put.

The semantic patch that fixes this problem is as follows
(http://coccinelle.lip6.fr):

// <smpl>
@@
expression root,e;
local idexpression child;
iterator name for_each_child_of_node;
@@

 for_each_child_of_node(root, child) {
   ... when != of_node_put(child)
       when != e = child
+  of_node_put(child);
?  break;
   ...
}
... when != child
// </smpl>
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Acked-by: NLudovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Until now, if we found spurious irq in irq_handler, we only updated the
status in register but not the status in the code. Due to this the system
will got stuck dues to the infinite loop

[gregory.clement@bootlin.com: update comment and add fix and stable tags]
Fixes: 30ac0d3b ("pinctrl: armada-37xx: Add edge both type gpio irq support")
Cc: <stable@vger.kernel.org>
Signed-off-by: NTerry Zhou <bjzhou@marvell.com>
Reviewed-by: NGregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds the stern warning to the kerneldoc text of both
gpiochip_add_pin[group]_range() functions in hope of detering
developers from ever using them in their DeviceTree-supported
pinctrl drivers in the future.

For anyone affected: Please refer to Section 2.1 of
Documentation/devicetree/bindings/gpio/gpio.txt on how to
bind pinctrl and gpio drivers via the "gpio-ranges" property.
Signed-off-by: NChristian Lamparter <chunkeey@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Sven Eckelmann reported an issue with the current IPQ4019 pinctrl.
Setting up any gpio-hog in the device-tree for his device would
"kill the bootup completely":

| [    0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
| [    0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe
| [    1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517
| [    1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register
| [    1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip
| [    1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
| [    1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri

This was also verified on a RT-AC58U (IPQ4018) which would
no longer boot, if a gpio-hog was specified. (Tried forcing
the USB LED PIN (GPIO0) to high.).

The problem is that Pinctrl+GPIO registration is currently
peformed in the following order in pinctrl-msm.c:
	1. pinctrl_register()
	2. gpiochip_add()
	3. gpiochip_add_pin_range()

The actual error code -517 == -EPROBE_DEFER is coming from
pinctrl_get_device_gpio_range(), which is called through:
        gpiochip_add
            of_gpiochip_add
                of_gpiochip_scan_gpios
                    gpiod_hog
                        gpiochip_request_own_desc
                            __gpiod_request
                                chip->request
                                    gpiochip_generic_request
                                       pinctrl_gpio_request
                                          pinctrl_get_device_gpio_range

pinctrl_get_device_gpio_range() is unable to find any valid
pin ranges, since nothing has been added to the pinctrldev_list yet.
so the range can't be found, and the operation fails with -EPROBE_DEFER.

This patch fixes the issue by adding the "gpio-ranges" property to
the pinctrl device node of all upstream Qcom SoC. The pin ranges are
then added by the gpio core.

In order to remain compatible with older, existing DTs (and ACPI)
a check for the "gpio-ranges" property has been added to
msm_gpio_init(). This prevents the driver of adding the same entry
to the pinctrldev_list twice.
Reported-by: NSven Eckelmann <sven.eckelmann@openmesh.com>
Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019]
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NChristian Lamparter <chunkeey@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add new files for the entry
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The .name field has been not being used in existent code logic, so
it's better that we remove them all.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

So far, EINT on each SoC all used exactly identical register map and thus
it's better that we apply generic register map already supported in EINT
library and stop copy-n-pasting the same data block and filling into its
platform data.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add EINT support to MT7622 SoC and the support is made as just an option
to MT7622 pinctrl.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch is in preparation for adding EINT support to MT7622 pinctrl,
and the refactoring doesn't alter any existent logic.

A reason we have to refactor EINT code pieces into a generic way is that
currently, they're tightly coupled with a certain type of MediaTek pinctrl
would cause a grown in a very bad way as there is different types of
pinctrl devices getting to join.

Therefore, it is an essential or urgent thing that EINT code pieces are
refactored to eliminate any dependencies across GPIO and EINT as possible.

Additional structure mtk_eint_[xt, hw, regs] are being introduced for
indicating how maps being designed between GPIO and EINT hw number, how to
set and get GPIO state for a certain EINT pin, what characteristic on a
EINT device is present on various SoCs.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Extend the capability of MT7622 pinctrl with adding EINT so that each
GPIO can be used to notify CPU when a signal state is changing on the
line as an external interrupt.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Merge tag 'samsung-pinctrl-4.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

Samsung pinctrl drivers changes for v4.18

1. Driver expects specific order of GPIO interrupt banks.  For S5Pv220
   and Exynos5410 this order was not preserved so fix and document it.
2. Remove support for Exynos5440 (tree-wide, support is dropped because
   there are no real users of this platform, it also did not get testing
   since long time).
3. Fix lost state of GPF1..5 pins on Exynos5433 during system suspend.

Merge tag 'sh-pfc-for-v4.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.18 (take two)

  - Add support for the new R-Car E3 SoC,
  - Add I2C pin groups on R-Car M3-N,
  - Small fixes and cleanups.

GPF1..5 banks in Exynos5433 are located in two pinctrl devices: ALIVE and
IMEM. Although they are partially located in ALIVE section, the state of
their registers in IMEM section is lost after suspend/resume cycle. To
properly handle such case, those banks have to be defined with standard
'exynos5433_bank_type_off' type (with PINCFG_TYPE_CON_PDN and
PINCFG_TYPE_PUD_PDN register offsets). This automatically instructs
the generic Samsung pinctrl suspend/resume code to save and restore state
of those registers.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

The comment block explaining the rationale for static pins contains
grammar errors.  It appeared first in the pin control driver for R-Car
H3 ES1.x, and spread to R-Car M3-W, H3 ES2.0, and M3-N later.

Fix the grammar in all copies at once.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds group and function of AVB PHY, LINK, MAGIC, MII and PTP
pins for the R8A77990 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds I2C{1,2,4,5,6,7} pins, groups and functions to
the R8A77990 SoC.

NOTE: I2C0 and I2C3 are not pin multiplexed.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77990
SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch implements control of pull-up and pull-down. On this SoC there
is no simple mapping of GP pins to bias register bits, so we need a table.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds initial pinctrl driver to support for the R8A77990 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This follows the style of existion PORT_GP_X macros and
will be used by a follow-up patch for the r8a77990 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Use the appropriate SPDX license identifier in the berlin pinctrl
driver source file and drop the previous license text.
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Could only support PIN_CONFIG_INPUT_DEBOUNCE now as the HW block
is too simple to support others. But even wrt. debounce capability,
it now could only support very limited period of time to satisfy the
real usecase. But still be useful to enable the crippled HW debounce
to prevent any spurious glitches from waking up the system if the
gpio is conguired as wakeup interrupt source.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There are 4 banks (GPIO0 ~ GPIO3), bank0 is in PD_PMU
subsystem, bank1/bank2/bank3 are in PD_BUS subsystem.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Armada 98dx3236 SoCs don't have a different MPP sel value for nand
specific pins so "dev" was technically correct. But all the other Armada
SoCs use "nand" in their dts and the pin is specific to the nand
interface so use "nand" for the function name.
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: NGregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add S900 pinctrl entries under ARCH_ACTIONS
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add gpio support to pinctrl driver for Actions Semi S900 SoC.
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add gpio bindings for Actions Semi S900 SoC.
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds a pair of context save/restore functions to save/restore the
state of a set of pinctrl registers. The context is lost during rtc only
suspend with ddr in self-refresh on am43xx. Currently the save/restore
is being done unconditionally. This will be optimized later with a
pdata-quirk function which will allow is to save/restore only when doing
the rtc only mode with ddr in self refresh.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The data pin 0-7 of the NAND controller are actually missing from
the nand pinctrl group, so we fix it here.

Fixes: 0f15f500 ("pinctrl: meson: Add GXL pinctrl definitions")
Reported-by: NLiang Yang <liang.yang@amlogic.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The data pin 0-7 of the NAND controller are actually missing from
the nand pinctrl group, so we fix it here.

Fixes: cd1e3b01 ("pinctrl: amlogic: gxbb: add nand pins")
Reported-by: NLiang Yang <liang.yang@amlogic.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

I was debugging some gpio issues and I thought that the output of gpio
debugfs was telling me the high or low level of the gpios with a '1' or
a '0'. We saw a line like this though:

 gpio93  : in 4 2mA pull down

and I started to think that there may be a gas leak in the building
because '4' doesn't mean high or low, and other pins said '0' or '1'. It
turns out, '4' is the function selection for the pinmux of the gpio and
not the value on the pin. Reading code helps decipher what debugfs is
actually saying.

Add support to read the input or output pin depending on how the pin is
configured so we can easily see the high or low value of the pin in
debugfs. Now the output looks like

 gpio93  : in   low  func4 2mA pull down

which clearly shows that the pin is an input, low, with function 4 and a
2mA drive strength plus a pull down.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The "dev" function is selected with the value 0x4 not 0x01.

Fixes: commit d7ae8f8d ("pinctrl: mvebu: pinctrl driver for 98DX3236 SoC")
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

DebugFS strings about pin pull status for no_keeper SoC are wrong

Fix this by adding a different string array for no_keeper SoC
Signed-off-by: NClément Péron <peron.clem@gmail.com>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks.
Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so
that main clk-controller driver could get an actual parent clock for the
CDEV1/2 clocks.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Reviewed-by: NMarcel Ziswiler <marcel@ziswiler.com>
Tested-by: NMarcel Ziswiler <marcel@ziswiler.com>
Tested-by: NMarc Dietrich <marvin24@gmx.de>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.

Add support for it.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The new helper returns index of the matching string in an array.
We are going to use it here.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Properties to set initial value of pin output buffer.
This can be useful for configure hardware in overlay files, and in early
boot for checking it states in QA sanity tests.
Signed-off-by: NMatheus Castello <matheus@castello.eng.br>
Reviewed-by: NEric Anholt <eric@anholt.net>
Acked-by: NStefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>