1. 04 8月, 2015 1 次提交
    • T
      Revert "libata: Implement support for sense data reporting" · 84ded2f8
      Tejun Heo 提交于
      This reverts commit fe7173c2.
      
      As implemented, ACS-4 sense reporting for ATA devices bypasses error
      diagnosis and handling in libata degrading EH behavior significantly.
      Revert the related changes for now.
      
      ATA_ID_COMMAND_SET_3/4 constants are not reverted as they're used by
      later changes.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Cc: Hannes Reinecke <hare@suse.de>
      Cc: stable@vger.kernel.org #v4.1+
      84ded2f8
  2. 03 8月, 2015 1 次提交
  3. 29 7月, 2015 1 次提交
  4. 17 7月, 2015 1 次提交
  5. 15 7月, 2015 6 次提交
  6. 19 6月, 2015 1 次提交
  7. 18 6月, 2015 2 次提交
  8. 17 6月, 2015 2 次提交
    • R
      ahci: Add support for Cavium's ThunderX host controller · b7ae128d
      Robert Richter 提交于
      This patch adds support for Cavium's ThunderX host controller. The
      controller resides on the SoC and is a AHCI compatible SATA controller
      with one port, compliant with Serial ATA 3.1 and AHCI Revision 1.31.
      There can exists multiple SATA controllers on the SoC.
      
      The controller depends on MSI-X support since the PCI ECAM controller
      on the SoC does not implement MSI nor lagacy intx interrupt support.
      Thus, during device initialization, if MSI fails MSI-X will be used to
      enable the device's interrupts.
      
      The controller uses non-standard BAR0 for its register range. The
      already existing device lookup (vendor and device id) that is already
      implemented for other host controllers is used to change the PCI BAR.
      Signed-off-by: NRobert Richter <rrichter@cavium.com>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      b7ae128d
    • R
      ahci: Add generic MSI-X support for single interrupts to SATA PCI driver · ee2aad42
      Robert Richter 提交于
      This patch adds generic MSI-X support for single interrupts to the
      SATA PCI driver. MSI-X support is needed for host controller that only
      have MSI-X support implemented, but no MSI or intx. This patch only
      adds support for single interrupts, multiple per-port MSI-X interrupts
      are not yet implemented.
      
      The new implementation still initializes MSIs first. Only if that
      fails, the code tries to enable MSI-X. If that fails too, setup is
      continued with intx interrupts.
      
      To not break other chips by this generic code change, there are the
      following precautions:
      
       * Interrupt ranges are not enabled at all.
      
       * Only single interrupt mode is enabled for msix cap devices. Thus,
         only one interrupt will be setup.
      
       * During the discussion with Tejun we agreed to change the init
         sequence from msix-msi-intx to msi-msix-intx. Thus, if a device
         offers msi and init does not fail, the msix init code will not be
         executed. This is equivalent to current code.
      
      With this, the code only setups single mode msix as a last resort if
      msi fails. No interrupt range is enabled at all. Only one interrupt
      will be enabled.
      
      tj: comment edits.
      
      Changes of the patch series:
      
      v5:
       * updated patch subject that the patch only implements single IRQ
       * moved Cavium specific code to a separate patch
       * detect Cavium ThunderX device with PCI_CLASS_STORAGE_SATA_AHCI
         instead of vendor/dev id
       * added more comments to the code
       * enable single msix support for all kind of devices (removing strict
         check)
       * rebased onto update libata/for-4.2 with patch 1, 2 applied
      
      v4:
       * removed implementation of ahci_init_intx()
       * improved patch descriptions
       * rebased onto libata/for-4.2
      
      v3:
       * store irq number in struct ahci_host_priv
       * change initialization order from msix-msi-intx to msi-msix-intx
       * improve comments in ahci_init_msix()
       * improve error message in ahci_init_msix()
       * do not enable MSI-X if MSI is actively disabled for the device
      
      v2:
       * determine irq vector from pci_dev->msi_list
      
      Based on a patch from Sunil Goutham <sgoutham@cavium.com>.
      Signed-off-by: NRobert Richter <rrichter@cavium.com>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      ee2aad42
  9. 10 6月, 2015 2 次提交
  10. 09 6月, 2015 1 次提交
  11. 08 6月, 2015 1 次提交
  12. 03 6月, 2015 2 次提交
    • R
      ahci: Store irq number in struct ahci_host_priv · 21bfd1aa
      Robert Richter 提交于
      Currently, ahci supports only msi and intx. To also support msix the
      handling of the irq number need to be changed. The irq number for msix
      devices is taken from msi_list instead of pci_dev. Thus, the irq
      number of a device needs to be stored in struct ahci_host_priv now.
      This allows the host controller to be activated in a generic way.
      
      This change is only intended for ahci drivers. For that reason the irq
      number is stored in struct ahci_host_priv used only by ahci drivers.
      Thus, the ABI changes only for ahci_host_activate(), but existing ata
      drivers (about 50) are unaffected and keep unchanged. All users of
      ahci_host_activate() have been updated.
      
      While touching drivers/ata/libahci.c, doing a small code cleanup in
      ahci_port_start().
      Signed-off-by: NRobert Richter <rrichter@cavium.com>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      21bfd1aa
    • R
      ahci: Move interrupt enablement code to a separate function · a1c82311
      Robert Richter 提交于
      This patch refactors ahci_init_interrupts() and moves msi code to a
      separate function. Need the split since we add msix initialization in
      a later patch. The initialization for msix will be done after msi but
      before intx.
      Signed-off-by: NRobert Richter <rrichter@cavium.com>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      a1c82311
  13. 29 5月, 2015 1 次提交
  14. 27 5月, 2015 1 次提交
  15. 26 5月, 2015 1 次提交
  16. 25 5月, 2015 1 次提交
  17. 22 5月, 2015 2 次提交
  18. 20 5月, 2015 1 次提交
  19. 19 5月, 2015 1 次提交
  20. 11 5月, 2015 1 次提交
    • S
      ata: ahci_xgene: Add AHCI Support for 2nd HW version of APM X-Gene SoC AHCI SATA Host controller. · c9802a4b
      Suman Tripathi 提交于
      This patch enables full AHCI feature support for APM X-Gene SoC SATA
      host controller. The following errata's are removed:
      
      1. 2a0bdff6 ("ahci-xgene: fix the dma state machine lockup for the
                       IDENTIFY DEVICE PIO mode command")
      2. 09c32aaa ("ahci_xgene: Fix the dma state machine lockup for the
                       ATA_CMD_SMART PIO mode command")
      3. 1540035d ("ahci_xgene: Implement the xgene_ahci_poll_reg_val to
                       support PMP")
      4. a3a84bc7 ("ahci_xgene: Implement the workaround to support PMP
                       enumeration and discovery")
      5. 1102407b ("ahci_xgene: Fix the DMA state machine lockup for the
                       ATA_CMD_PACKET PIO mode command")
      6. 72f79f9e ("ahci_xgene: Removing NCQ support from the APM X-Gene
      		SoC AHCI SATA Host Controller driver")
      
      In addition, enable PMP support for APM X-Gene SoC and enable FBS
      support for second generation APM X-Gene SoC.
      Signed-off-by: NSuman Tripathi <stripathi@apm.com>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      c9802a4b
  21. 10 5月, 2015 3 次提交
  22. 05 5月, 2015 5 次提交
  23. 03 5月, 2015 1 次提交
  24. 26 4月, 2015 1 次提交