After the patch series for system suspending support, tegra_idle_lp2_last()
no longer uses its parameters cpu_on_time or cpu_off_time, so remove them.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding suspend to RAM support for Tegra platform. There are three suspend
mode for Tegra. The difference were below.

* LP2: CPU voltage off
* LP1: CPU voltage off, DRAM in self-refresh
* LP0: CPU + Core voltage off, DRAM in self-refresh

After this patch, the LP2 suspend mode will be supported.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The PMC mostly controls the entry and exit of the system from different
sleep modes. Different platform or system may have different configurations.
The power management configurations of PMC is represented as some properties.
The system needs to define the properties when the system supports deep sleep
mode (i.e. suspend).

Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the wake up handling for legacy irq controller, and using
IRQCHIP_MASK_ON_SUSPEND for wake irq handling.

Based on the work by:
Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The CPU power timer set up function was related to PMC register. Now moving
it to PMC driver. And it also help to clean up the PM related code later.

The timer was calculated based on the input clock of PMC. In this patch, we
also get the clock from DT.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add speedo-based process identification for Tegra114.

Based on the work by: Alex Frid <afrid@nvidia.com>
Signed-off-by: NDanny Huang <dahuang@nvidia.com>
[swarren: added include of bug.h]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Expose Tegra chip ID and revision in /sys/devices/soc for user mode
usage
Signed-off-by: NDanny Huang <dahuang@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The secondary CPU can be brought up by toggling the power in PMC. Then
the flow controller will release CPU to go by clearing the reset and
clamp signal automatically.

Based on the work by:
Bo Yan <byan@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Using the CPU power on function in PMC driver to bring up secondary CPUs,
because we are going to re-factor powergate driver to support generic
power domain. It will be removed later and added the generic power domain
support in PMC driver.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding the power on function for secondary CPUs in PMC driver, this can
help us to remove legacy powergate driver and add generic power domain
support later.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Tegra kernel only support boot from DT now. Clean up the PMC driver
to support DT only, that includes:

* remove the ifdef of CONFIG_OF
* replace the static mapping of PMC addr to map from DT
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The PMC HW is not 100% compatible across all Tegra series. We need to
specify each of them in the DT match table.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

"tegra_boot_secondary()" has many condition branches for some Tegra
SoC generations in a single function so that it's not easy to compile
a kernel only for a single SoC if one wants with some reason, debug
purpose(?). This patch provides SoC specific version of
boot_secondary(), tegra{20,30}_boot_secondary(). This could allow
any combination of SoC to be built. Those boot_secondary functions can
be preparation when we ntroduce chip specific function pointers in the
future without having chip dependent branches around.

Also removed unused definition/prototpye.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
[josephl: remove the Tegra114 part of the original patch]
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Unify board-dt-tegra{30,114} to the Tegra20 DT board file, "tegra.c".
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This is the preparation to unify "board-dt-tegra{20,30,114}.c" to a
single file "tegra.c".
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Refactored tegra{20,30,114}_init_early() so that we have the unified
tegra_init_early().
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This fixes:

arch/arm/mach-tegra/board-harmony-pcie.c: In function ‘harmony_pcie_init’:
arch/arm/mach-tegra/board-harmony-pcie.c:65:18: warning: ignoring return
    value of ‘regulator_enable’, declared with attribute
    warn_unused_result [-Wunused-result]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The warm boot sequence of Tegra30 secondary CPUs should wait for the
power ready then removing the clamps.

This did not fix any known or unknown issue, but nice to have this fix.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Check a return value for tegra_powergate_remove_clamping().
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

There is no need to unlock MMIO access to the DBGLAR all the time. Doing
so may even cause problems if a SW bug causes writes to that MMIO region.

Cortex-A15 processors do not support the CP14 register write the code
currently uses to unlock the DBGLAR; the instruction throws an undefined
instruction exceptions. This prevents tegra_secondary_startup() from
executing on Tegra114, and hence prevents SMP.

Remove the code that unlocks this access.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Prior to this change, {save,restore}_cpu_arch_register() collaborated to
maintain the value of the CPU diagnostic register across power cycles.
This was required to maintain any CPU errata workaround enable bits in
that register. However, now that the Tegra reset vector code always
enables all required workarounds, there is no need to save and restore
the diagnostic register; it is always explicitly programmed in the
required manner.

Hence, remove the save/restore logic.

This has the advantage that the kernel always directly controls the value
of this register every boot, rather than relying on a bootloader or other
kernel code having previously written the correct value into it. This
makes CPU0 (which was previously saved/restored) and CPUn (which should
have been set up by the reset vector) be controlled in exactly the same
way, which is easier to debug/find/...

In particular, when converting Tegra to a multi-platform kernel, the CPU0
diagnostic register value initially comes from the bootloader. Most Tegra
bootloaders don't yet enable all required CPU bug workarounds. The
previous commit updates the kernel to do so on any CPU power cycle.
However, the save/restore code ends up over-writing the value with the
old bootloader-driven value instead of the now more-likely-to-be-correct
kernel value!

Even irrespective of multi-platform conversion, this change limits the
kernel's exposure to any WARs the bootloader didn't enable for CPU0: on
the very first LP2 transition (CPU power-saving which power-cycles the
CPU), the correct value will be enabled.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The CPU cores in Tegra contain some errata. Workarounds must be applied
for these every time a CPU boots. Implement those workarounds directly
in the Tegra-specific CPU reset vector.

Many of these workarounds duplicate code in the core ARM kernel.

However, the core ARM kernel cannot enable those workarounds when
building a multi-platform kernel, since they require writing to secure-
only registers, and a multi-platform kernel often does not run in secure
mode, and also cannot generically/architecturally detect whether it is
running in secure mode, and hence cannot either unconditionally or
conditionally apply these workarounds.

Instead, the workarounds must be applied in architecture-specific reset
code, which is able to have more direct knowledge of the secure/normal
state. On Tegra, we will be able to detect this using a non-architected
register in the future, although we currently assume the kernel runs only
in secure mode. Other SoCs may never run the kernel in secure mode, and
hence always rely on a secure monitor to enable the workarounds, and
hence never implement them in the kernel.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

mach-socfpga is another platform that needs to use
v7_invalidate_l1 to bringup additional cores. There was a comment that
the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: NPavel Machek <pavel@denx.de>
Tested-by: NStephen Warren <swarren@nvidia.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Olof Johansson <olof@lixom.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The Kconfig options selected by ARCH_TEGRA_*_SOC were recently sorted.
Update the newly added ARCH_TEGRA_114_SOC's select statements to match.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

CONFIG_ARCH_TEGRA_114_SOC doesn't currently enable gpiolib, which causes
numerous build problems building a Tegra kernel with only Tegra114
enabled, and not Tegra20 or Tegra30. Enable ARCH_REQUIRE_GPIOLIB to
solve this. However, all Tegra will use gpiolib, so select this option
from ARCH_TEGRA rather than each individual ARCH_TEGRA_*_SOC, to
prevent this problem for any future chips.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch fixes the build error when ARCH_TEGRA_114_SOC is enabled
and ARCH_TEGRA_3x_SOC is disabled.

This provides Tegra114 with its own tegra114_init_early() instead of
making use of tegra30_init_early() so that T114 build doesn't depend
on T3x anymore.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Fix build error in board-dt-tegra114.c(next-20130204)
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Reported-by: Sami Liedes<sliedes@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Based on two separate cleanup branches, it's now empty and can be removed.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Cc: Stephen Warren <swarren@wwwdotorg.org>

policy->shared_type field was added only for SoCs with ACPI support:

commit 3b2d9942
Author: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Date:   Wed Dec 14 15:05:00 2005 -0500

    P-state software coordination for ACPI core

    http://bugzilla.kernel.org/show_bug.cgi?id=5737

Many non-ACPI systems are filling this field by mistake, which makes its usage
confusing. Lets clean it.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

For multicore SoC's, with cores sharing clock line, we are required to set
policy->cpus and policy->related_cpus with mask of cpus.

With following patch, we need to set policy->cpus with mask of all possible cpus
and policy->related_cpus would be filled automatically by the cpufreq core.

commit 4948b355e90080cd5ec1e91189f65a01e4186ef2
Author: Viresh Kumar <viresh.kumar@linaro.org>
Date:   Tue Jan 29 14:39:08 2013 +0000

    cpufreq: Simplify cpufreq_add_dev()

Current Tegra driver fills only ->related_cpus and not ->cpus, which looks to be
incorrect. Lets fix it.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Select PINCTRL and PINCTRL_TEGRA114 for enabling Tegra114 pincontrol
driver for Tegra114 SoC.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding the generic ARM_CPUIDLE_WFI_STATE support for Tegra114.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add new Tegra 114 SoC support.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add tegra_chip_id TEGRA114 0x35
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one
core to go into this mode before other core. The coupled cpuidle framework
can help to sync the MPCore to coupled state then go into "powered-down"
idle mode together. The driver can just assume the MPCore come into
"powered-down" mode at the same time. No need to take care if the CPU_0
goes into this mode along and only can put it into safe idle mode (WFI).

The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI for waiting CPU0 in the same state.
When the CPU0 requests powered-down state, it attempts to put the secondary
CPU into reset to prevent it from waking up. Then power down both CPUs
together and power off the cpu rail.

Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".

Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NColin Cross <ccross@android.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI. The Tegra20 had a limition to
power down both CPU cores. The secondary CPU must waits for CPU0 in
powered-down state too. If the secondary CPU be woken up before CPU0
entering powered-down state, then it needs to restore its CPU states
and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".

Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it
include the power of GIC. That caused the SGI (Software Generated
Interrupt) been lost. Because the SGI can't wake up the CPU that in
the "powered-down" CPU idle mode. We need to check if there is any
pending SGI when go into "powered-down" CPU idle mode. This is important
especially when applying the coupled cpuidle framework into "power-down"
cpuidle dirver. Because the coupled cpuidle framework may have the
chance that misses IPI_SINGLE_FUNC handling sometimes.

For the PPI or SPI, something like the legacy peripheral interrupt. It
still can be maintained by Tegra legacy interrupt controller. If there
is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The
CPU can be woken up immediately. So we don't need to take care the same
situation for PPI or SPI.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

USB register base address and sizes defined in iomap.h
are not used in any files other than board-dt-tegra20.c.
Hence removed those defines from header file and using
the absolute values in board files.
Signed-off-by: NVenu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Remove AUXDATA as clocks are initialized from device node.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>