- 22 3月, 2016 1 次提交
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由 Sekhar Nori 提交于
Revert 5c3b99d0 ("PCI: dra7xx: Mark driver as broken"). 1c96bee4 ("ARM: DRA7: hwmod: Add custom reset handler for PCIeSS") added support to de-assert PCIe reset, so DRA7x PCIe is not broken anymore. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 15 3月, 2016 3 次提交
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由 Joao Pinto 提交于
Add a reference platform driver for PCI RC IP Protoyping Kits based on the ARC SDP. [bhelgaas: changelog, split patch up, MAINTAINERS update] Signed-off-by: NJoao Pinto <jpinto@synopsys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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由 Joao Pinto 提交于
Add a default DesignWare "link_up" test for use when a sub-driver doesn't supply its own pcie_host_ops.link_up() method. [bhelgaas: changelog, split into its own patch] Signed-off-by: NJoao Pinto <jpinto@synopsys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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由 Joao Pinto 提交于
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and spear13xx) had similar loops waiting for the link to come up. Add a generic dw_pcie_wait_for_link() for use by all these drivers so the waiting is done consistently, e.g., always using usleep_range() rather than mdelay() and using similar timeouts and retry counts. Note that this changes the Keystone link training/wait for link strategy, so we initiate link training, then wait longer for the link to come up before re-initiating link training. [bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c] Signed-off-by: NJoao Pinto <jpinto@synopsys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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- 12 3月, 2016 9 次提交
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由 David Daney 提交于
The cavium,pci-thunder-ecam devices are exactly ECAM-based PCI root complexes. These root complexes (loosely referred to as ECAM units in the hardware manuals) are used to access the Thunder on-chip devices. They are special in that all the BARs on devices behind these root complexes are at fixed addresses. Add a driver for these devices that synthesizes Enhanced Allocation (EA) capability entries for each BAR. Since this EA synthesis is needed for exactly two chip models, we can hard- code some assumptions about the device topology and the layout of the config space of specific DEVFNs in the driver. [bhelgaas: changelog, whitespace] Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NRob Herring <robh@kernel.org>
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由 David Daney 提交于
The root complexes used to access off-chip PCIe devices (called PEM units in the hardware manuals) on some Cavium ThunderX processors require quirky access methods for the config space of the PCIe bridge. Add a driver to provide these config space accessor functions. Use the pci-host-common code to configure the PCI machinery. Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NRob Herring <robh@kernel.org> Acked-by: NArnd Bergmann <arnd@arndb.de>
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由 David Daney 提交于
Move pci_host_common_probe() and associated functions to pci-host-common.c, where it can be shared with other drivers. Make it public (not static) and update Kconfig and Makefile to build it. No functional change intended. [bhelgaas: split into separate patch, changelog] Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NWill Deacon <will.deacon@arm.com>
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由 David Daney 提交于
Factor gen_pci_probe(), moving most of it into pci_host_common_probe() where it can be shared with other drivers that have slightly different config accessors. No functional change intended. [bhelgaas: split into separate patch, changelog] Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NWill Deacon <will.deacon@arm.com>
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由 David Daney 提交于
Move definitions for generic PCI host controller driver structures to a separate header file so we can share them with other drivers. No functional change intended. [bhelgaas: split into separate patch, changelog] Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NWill Deacon <will.deacon@arm.com>
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由 Bharat Kumar Gogada 提交于
Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP. [bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix] Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: NRavi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NRob Herring <robh@kernel.org>
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由 Shawn Lin 提交于
A SerDes PHY is optional, so if devm_phy_get() doesn't find one at all, that's fine. But if devm_phy_get() finds a PHY that doesn't have a driver yet, it returns -EPROBE_DEFER. In that case, defer probing the Keystone driver. We may be able to load it later after a PHY driver is loaded. [bhelgaas: changelog, check for -EPROBE_DEFER first] Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Ley Foon Tan 提交于
Originally altera_pcie_link_is_up() decided the link was up if any of the low four bits of the LTSSM register were set. But the link is only up if the LTSSM state is L0, so check for that exact value. [bhelgaas: changelog] Signed-off-by: NLey Foon Tan <lftan@altera.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Simon Horman 提交于
Make the R-Car drivers depend on ARCH_RENESAS instead of ARCH_SHMOBILE. This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS. The motivation is that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM-based SoCs. Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 09 3月, 2016 8 次提交
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由 Thierry Reding 提交于
BARs are disabled when the size register is 0, so it's misleading to write a base address into the start register. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Thierry Reding 提交于
Track the offsets of the bus -> CPU mapping for I/O and memory. This is cosmetic for current Tegra chips because the offset is always 0. But to properly support legacy use-cases, like VGA, this would be needed so that PCI bus addresses can be relocated. While at it, also request the I/O resource both in physical memory and I/O space to make /proc/iomem consistent, as well as add the I/O region to the list of host bridge resources. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Thierry Reding 提交于
The num_ports field of the tegra_pcie structure is never used so remove it. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Thierry Reding 提交于
The configuration space mapping on Tegra is somewhat special, and in order to avoid wasting virtual address space the configuration space for each bus needs to be stitched together from several blocks which form a single continuous virtual address range for accessors. Currently the configuration space is mapped upon the first access to one of its registers. However, the mapping operation may sleep under certain circumstances, so doing it from the configuration space accessors (they are protected by a spin lock) will trigger a warning. To avoid the warning, use the ->add_bus() callback to perform the mapping at enumeration time when the operation is allowed to sleep. Also add an implementation of ->remove_bus() that undoes the mapping established by the ->add_bus() callback. While it isn't currently possible to unload the module, there is work underway to remedy this, and this code will come in handy when that happens. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Bharat Kumar Gogada 提交于
Modify the Microblaze PCI subsystem to work with the generic drivers/pci/host/pcie-xilinx.c driver on Microblaze and Zynq. [bhelgaas: changelog] Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: NRavi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMichal Simek <michal.simek@xilinx.com>
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由 Bharat Kumar Gogada 提交于
The Xilinx AXI PCIe Host Bridge Soft IP driver was previously only supported on ARM (in particular, on ARCH_ZYNC), and pci_fixup_irqs() is available there. But Microblaze will do IRQ fixup in pcibios_add_device(), so pci_fixup_irqs() is not available on Microblaze. Don't call pci_fixup_irqs() on Microblaze, so the driver can work on both Zynq and Microblaze Architectures. [bhelgaas: revise changelog to show similarity to bdb8a184 ("PCI: iproc: Call pci_fixup_irqs() for ARM64 as well as ARM")] Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: NRavi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NMichal Simek <michal.simek@xilinx.com>
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由 Bharat Kumar Gogada 提交于
The Xilinx PCIe host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. [bhelgaas: revise changelog to show similarity to 79953dd2 ("PCI: rcar: Remove dependency on ARM-specific struct hw_pci")] Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: NRavi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NMichal Simek <michal.simek@xilinx.com>
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由 Bharat Kumar Gogada 提交于
Use the new of_pci_get_host_bridge_resources() API in place of the PCI OF DT parser. [bhelgaas: revise changelog to show similarity to 0021d22b ("PCI: designware: Use of_pci_get_host_bridge_resources() to parse DT")] Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: NRavi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NMichal Simek <michal.simek@xilinx.com>
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- 01 3月, 2016 3 次提交
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由 Justin Waters 提交于
The settings in GPR8 are dependent upon the particular layout of the hardware platform. As such, they should be configurable via the device tree. Look up PHY Tx driver settings from the device tree. Fall back to the original hard-coded values if they are not specified in the device tree. Signed-off-by: NJustin Waters <justin.waters@timesys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NLucas Stach <l.stach@pengutronix.de>
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由 Minghuan Lian 提交于
Some kinds of Layerscape PCIe controllers will forward the received message TLPs to system application address space, which could corrupt system memory or lead to a system hang. Enable MSG_DROP to fix this issue. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Murali Karicheri 提交于
Commit cbce7900 ("PCI: designware: Make driver arch-agnostic") changed the host bridge sysdata pointer from the ARM pci_sys_data to the DesignWare pcie_port structure, and changed pcie-designware.c to reflect that. But it did not change the corresponding code in pci-keystone-dw.c, so it caused crashes on Keystone: Unable to handle kernel NULL pointer dereference at virtual address 00000030 pgd = c0003000 [00000030] *pgd=80000800004003, *pmd=00000000 Internal error: Oops: 206 [#1] PREEMPT SMP ARM CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.2-00139-gb74f926 #2 Hardware name: Keystone PC is at ks_dw_pcie_msi_irq_unmask+0x24/0x58 Change pci-keystone-dw.c to expect sysdata to be the struct pcie_port pointer. [bhelgaas: changelog] Fixes: cbce7900 ("PCI: designware: Make driver arch-agnostic") Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.4+ CC: Zhou Wang <wangzhou1@hisilicon.com>
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- 27 2月, 2016 1 次提交
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由 Thierry Reding 提交于
This driver uses PCI glue that is only available on 32-bit ARM. This used to work fine as long as ARCH_MVEBU and ARCH_DOVE were exclusively 32-bit, but there's a patch in the pipe to make ARCH_MVEBU also available on 64-bit ARM. [bhelgaas: changelog; patch is coming but not merged yet] Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
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- 17 2月, 2016 1 次提交
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由 Jake Oshins 提交于
Add a new driver which exposes a root PCI bus whenever a PCI Express device is passed through to a guest VM under Hyper-V. The device can be single- or multi-function. The interrupts for the devices are managed by an IRQ domain, implemented within the driver. [bhelgaas: fold in race condition fix (http://lkml.kernel.org/r/1456340196-13717-1-git-send-email-jakeo@microsoft.com)] Signed-off-by: NJake Oshins <jakeo@microsoft.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 10 2月, 2016 2 次提交
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由 Lorenzo Pieralisi 提交于
The PCIe designware host driver is not used in system configurations requiring the PCI_PROBE_ONLY flag to be set to prevent resources assignment, therefore the driver code handling the flag can be removed from the kernel. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com> Acked-by: NJingoo Han Jingoo Han <jingoohan1@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com> Cc: Zhou Wang <wangzhou1@hisilicon.com>
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由 Jisheng Zhang 提交于
Some platforms don't support ATU, e.g., pci-keystone.c. These platforms use their own address translation component rather than ATU, and they provide the rd_other_conf and wr_other_conf methods to program the translation component and perform the access. Add a comment to explain why we don't program the ATU for these platforms. [bhelgaas: changelog] Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 06 2月, 2016 2 次提交
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由 Yang Shi 提交于
The Layerscape PCI host driver must recognize ls2085a compatible when using firmware with ls2085a compatible property, otherwise the PCI bus won't be detected even though ls2085a compatible is included by the dts. Signed-off-by: NYang Shi <yang.shi@linaro.org> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Lorenzo Pieralisi 提交于
The PCIe rcar host driver is not used in system configurations requiring the PCI_PROBE_ONLY flag to be set to prevent resources assignment, therefore the driver code handling the flag can be removed from the kernel. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NSimon Horman <horms+renesas@verge.net.au> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Phil Edworthy <phil.edworthy@renesas.com>
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- 28 1月, 2016 1 次提交
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由 Ray Jui 提交于
Commit 943ebae7 ("PCI: iproc: Add PAXC interface support") only allowed device 0, which is a regression on BCMA-based platforms. All systems support only one device, a Root Port at 00:00.0, on the root bus. PAXC-based systems support only the Root Port (00:00.0) and a single device (with multiple functions) below it, e.g., 01:00.0, 01:00.1, etc. Non-PAXC systems support arbitrary devices below the Root Port. [bhelgaas: changelog, fold in removal of MAX_NUM_PAXC_PF check] Fixes: 943ebae7 ("PCI: iproc: Add PAXC interface support") Reported-by: NRafal Milecki <zajec5@gmail.com> Signed-off-by: NRay Jui <rjui@broadcom.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 26 1月, 2016 4 次提交
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由 Lucas Stach 提交于
imx6_pcie_link_up() previously used usleep_range() to wait for the link to come up. Since it may be called while holding the config spinlock, the sleep causes a "BUG: scheduling while atomic" error. Instead of waiting for the link to come up in imx6_pcie_link_up(), do the waiting in imx6_pcie_wait_for_link(), where we're not holding a lock and sleeping is allowed. [bhelgaas: changelog, references to bugzilla and f95d3ae7] Link: https://bugzilla.kernel.org/show_bug.cgi?id=100031 Fixes: f95d3ae7 ("PCI: imx6: Wait for retraining") Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Lucas Stach 提交于
Remove the remnants of the workaround for erratum ERR005184 which was never completely implemented. The checks alone don't carry any value as we don't act properly on the result. A workaround should be added to the lane speed change in establish_link later. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Lucas Stach 提交于
This adds the PHY reset into a common error path of imx6_pcie_establish_link(), deduplicating some of the debug prints. Also reduce the severity of the "no-link" message in the one place where it is expected to be hit when no peripheral is attached. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Lucas Stach 提交于
Move imx6_pcie_reset_phy() near the other PHY related functions in the file. This is a cosmetic change, but also allows to do the following changes without introducing needless forward declarations. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 11 1月, 2016 3 次提交
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由 Phil Edworthy 提交于
For PCIe compliance, the PHY registers need setting as per the manual. Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
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由 Phil Edworthy 提交于
If runtime PM is enabled in the kernel config, simply enable the clocks once during probe. Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
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由 Bjorn Helgaas 提交于
Drivers based on the DesignWare core can override the config read accessors by supplying rd_own_conf() and rd_other_conf() function pointers. dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root bus) or dw_pcie_rd_other_conf(): dw_pcie_rd_conf dw_pcie_rd_own_conf # if on root bus dw_pcie_rd_other_conf # if not on root bus Previously we checked for rd_other_conf() directly in dw_pcie_rd_conf(), but we checked for rd_own_conf() in dw_pcie_rd_own_conf(). Check for rd_other_conf() in dw_pcie_rd_other_conf() to make this symmetric with the rd_own_conf() checking, and similarly for the write path. No functional change intended. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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- 09 1月, 2016 2 次提交
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由 Phil Edworthy 提交于
The pci_sys_data struct was previously used by pci_common_init_dev() and by the ARM pcibios_align_resource(), but recent commits removed those uses: cbce7900 ("PCI: designware: Make driver arch-agnostic") b3a72384 ("ARM/PCI: Replace pci_sys_data->align_resource with global function pointer") cbce7900 removed the use of pci_common_init_dev() by DesignWare drivers, including pcie-rcar.c, and b3a72384 removed the use of struct pci_sys_data by the ARM pcibios_align_resource(). Remove struct pci_sys_data from pcie-rcar.c. [bhelgaas: changelog] Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Gabriele Paoloni 提交于
Add support for the HiSilicon Hip06 SoC. Documentation has been updated to include Hip06. Add Gabriele Paoloni as maintainer of the driver. Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NZhou Wang <wangzhou1@hisilicon.com>
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