- 07 2月, 2017 5 次提交
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由 Rob Clark 提交于
Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
Suggested by Rob Herring. We still support the old names for compatibility with downstream android dt files. Cc: Rob Herring <robh@kernel.org> Signed-off-by: NRob Clark <robdclark@gmail.com> Reviewed-by: NEric Anholt <eric@anholt.net> Acked-by: NRob Herring <robh@kernel.org>
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由 Rob Clark 提交于
This was never documented or used in upstream dtb. It is used by downstream bindings from android device kernels. But the quirks are a property of the gpu revision, and as such are redundant to be listed separately in dt. Instead, move the quirks to the device table. Signed-off-by: NRob Clark <robdclark@gmail.com> Reviewed-by: NEric Anholt <eric@anholt.net>
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由 Rob Clark 提交于
The original way we determined the gpu version was based on downstream bindings from android kernel. A cleaner way is to get the version from the compatible string. Note that no upstream dtb uses these bindings. But the code still supports falling back to the legacy bindings (with a warning), so that we are still compatible with the gpu dt node from android device kernels. Signed-off-by: NRob Clark <robdclark@gmail.com> Reviewed-by: NEric Anholt <eric@anholt.net> Acked-by: NRob Herring <robh@kernel.org>
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由 Rob Clark 提交于
The plan is to use the OPP bindings. For now, remove the documentation for qcom,gpu-pwrlevels, and make the driver fall back to a safe low clock if the node is not present. Note that no upstream dtb use this node. For now we keep compatibility with this node to avoid breaking compatibility with downstream android dt files. Signed-off-by: NRob Clark <robdclark@gmail.com> Reviewed-by: NEric Anholt <eric@anholt.net> Acked-by: NRob Herring <robh@kernel.org>
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- 13 1月, 2017 2 次提交
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由 Rob Clark 提交于
Fixes: 9cb07b099fb ("drm/msm: support multiple address spaces") Reported-by: NRiku Voipio <riku.voipio@linaro.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
It would race between userspace thread and commit worker. Ie. vblank irq would trigger event and userspace could begin the next atomic update, before the commit worker had a chance to clear the pending flag. If we do end up needing something to prevent userspace from trying another pageflip before getting vblank event, it should probably be implemented as a pending_planes bitmask, similar to pending_crtcs. See start_atomic() and end_atomic(). Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 12 1月, 2017 2 次提交
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由 Daniel Vetter 提交于
This is the deprecated function for when you embedded the framebuffer somewhere else (which breaks refcounting). But msm is using drm_framebuffer_remove and a free-standing fb, so this is rendundant. Cc: Rob Clark <robdclark@gmail.com> Reviewed-by: NArchit Taneja <architt@codeaurora.org> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1482835765-12044-1-git-send-email-daniel.vetter@ffwll.ch
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由 Arnd Bergmann 提交于
Many DRM drivers only work with an MMU, and after the patch to enable core DRM support without MMU, we already had one fixup for many of them. The etnaviv, armada and msm drivers were missed and have the same problem: warning: (DRM_ETNAVIV) selects IOMMU_SUPPORT which has unmet direct dependencies (MMU) warning: (DRM_I915 && DRM_MSM && DRM_ETNAVIV) selects SHMEM which has unmet direct dependencies (MMU) drivers/gpu/drm/armada/armada_gem.o: In function `armada_gem_vm_fault': armada_gem.c:(.text.armada_gem_vm_fault+0x14): undefined reference to `vm_insert_pfn' arch/arm/mm/dma-mapping.c: In function '__iommu_alloc_remap': arch/arm/mm/dma-mapping.c:1390:4: error: 'VM_ARM_DMA_CONSISTENT' undeclared (first use in this function) arch/arm/mm/dma-mapping.c:1456:31: error: 'atomic_pool' undeclared (first use in this function); did you mean 'atomic_xor'? Fixes: 011cda58 ("drm: fix compilations issues introduced by "drm: allow to use mmuless SoC"") Fixes: 62a0d98a ("drm: allow to use mmuless SoC") Signed-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170111133357.3664191-2-arnd@arndb.de
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- 30 12月, 2016 4 次提交
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由 Daniel Vetter 提交于
Including all drivers. I thought about keeping small compat functions to avoid having to change all drivers. But I really like the drm_printer idea, so figured spreading it more widely is a good thing. v2: Review from Chris: - Natural argument order and better name for drm_mm_print. - show_mm() macro in the selftest. Cc: Rob Clark <robdclark@gmail.com> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jyri Sarha <jsarha@ti.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1483009764-8281-1-git-send-email-daniel.vetter@ffwll.ch
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由 Jordan Crouse 提交于
For every submission buffer object one of MSM_SUBMIT_BO_WRITE and MSM_SUBMIT_BO_READ must be set (and nothing else). If we allowed zero then the buffer object would never get queued to be unreferenced. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Jordan Crouse 提交于
The error cases in submit_reloc() need to put back the virtual address of the bo before failling. Add a single failure path for the function. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Jordan Crouse 提交于
Currently the value written to CP_RB_WPTR is calculated on the fly as (rb->next - rb->start). But as the code is designed rb->next is wrapped before writing the commands so if a series of commands happened to fit perfectly in the ringbuffer, rb->next would end up being equal to rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR. The easiest way to fix this is to mask WPTR when writing it to the hardware; it makes the hardware happy and the rest of the ringbuffer math appears to work and there isn't any point in upsetting anything. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> [squash in is_power_of_2() check] Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 18 12月, 2016 1 次提交
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由 Laurent Pinchart 提交于
Instead of linking encoders and bridges in every driver (and getting it wrong half of the time, as many drivers forget to set the drm_bridge encoder pointer), do so in core code. The drm_bridge_attach() function needs the encoder and optional previous bridge to perform that task, update all the callers. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Stefan Agner <stefan@agner.ch> # For DCU Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> # For atmel-hlcdc Acked-by: Vincent Abriou <vincent.abriou@st.com> # For STI Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> # For sun4i Acked-by: Xinliang Liu <z.liuxinliang@hisilicon.com> # For hisilicon Acked-by: Jyri Sarha <jsarha@ti.com> # For tilcdc Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NArchit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/1481709550-29226-4-git-send-email-laurent.pinchart+renesas@ideasonboard.com
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- 15 12月, 2016 5 次提交
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由 Ville Syrjälä 提交于
Replace uses of fb->pixel_format with fb->format->format. Less duplicated information is a good thing. Note that coccinelle failed to eliminate the "/* fourcc format */" comment from drm_framebuffer.h, so I had to do that part manually. @@ struct drm_framebuffer *FB; expression E; @@ drm_helper_mode_fill_fb_struct(...) { ... - FB->pixel_format = E; ... } @@ struct drm_framebuffer *FB; expression E; @@ i9xx_get_initial_plane_config(...) { ... - FB->pixel_format = E; ... } @@ struct drm_framebuffer *FB; expression E; @@ ironlake_get_initial_plane_config(...) { ... - FB->pixel_format = E; ... } @@ struct drm_framebuffer *FB; expression E; @@ skylake_get_initial_plane_config(...) { ... - FB->pixel_format = E; ... } @@ struct drm_framebuffer *a; struct drm_framebuffer b; @@ ( - a->pixel_format + a->format->format | - b.pixel_format + b.format->format ) @@ struct drm_plane_state *a; struct drm_plane_state b; @@ ( - a->fb->pixel_format + a->fb->format->format | - b.fb->pixel_format + b.fb->format->format ) @@ struct drm_crtc *CRTC; @@ ( - CRTC->primary->fb->pixel_format + CRTC->primary->fb->format->format | - CRTC->primary->state->fb->pixel_format + CRTC->primary->state->fb->format->format ) @@ struct drm_mode_set *set; @@ ( - set->fb->pixel_format + set->fb->format->format | - set->crtc->primary->fb->pixel_format + set->crtc->primary->fb->format->format ) @@ @@ struct drm_framebuffer { ... - uint32_t pixel_format; ... }; v2: Fix commit message (Laurent) Rebase due to earlier removal of many fb->pixel_format uses, including the 'fb->format = drm_format_info(fb->format->format);' snafu v3: Adjusted the semantic patch a bit and regenerated due to code changes Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481751175-18463-1-git-send-email-ville.syrjala@linux.intel.com
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由 Ville Syrjälä 提交于
Replace uses of fb->depth with fb->format->depth. Less duplicate information is a good thing. @@ struct drm_framebuffer *fb; expression E; @@ drm_helper_mode_fill_fb_struct(...) { ... - fb->depth = E; ... } @@ struct nouveau_framebuffer *fb; @@ - fb->base.depth + fb->base.format->depth @@ struct drm_framebuffer fb; @@ - fb.depth + fb.format->depth @@ struct drm_framebuffer *fb; @@ - fb->depth + fb->format->depth @@ struct drm_framebuffer fb; @@ - (fb.format->depth) + fb.format->depth @@ struct drm_framebuffer *fb; @@ - (fb->format->depth) + fb->format->depth @@ @@ struct drm_framebuffer { ... - unsigned int depth; ... }; v2: Drop the vmw stuff (Daniel) Rerun spatch due to code changes Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1481751095-18249-1-git-send-email-ville.syrjala@linux.intel.com
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由 Ville Syrjälä 提交于
Replace drm_format_num_planes(fb->pixel_format) with just fb->format->num_planes. Avoids the expensive format info lookup. @@ struct drm_framebuffer *a; struct drm_framebuffer b; @@ ( - drm_format_num_planes(a->pixel_format) + a->format->num_planes | - drm_format_num_planes(b.pixel_format) + b.format->num_planes ) @@ struct drm_plane_state *a; struct drm_plane_state b; @@ ( - drm_format_num_planes(a->fb->pixel_format) + a->fb->format->num_planes | - drm_format_num_planes(b.fb->pixel_format) + b.fb->format->num_planes ) @@ struct drm_framebuffer *a; identifier T; @@ T = a->pixel_format <+... - drm_format_num_planes(T) + a->format->num_planes ...+> @@ struct drm_framebuffer b; identifier T; @@ T = b.pixel_format <+... - drm_format_num_planes(T) + b.format->num_planes ...+> v2: Rerun spatch due to code changes Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Suggested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481751022-18015-1-git-send-email-ville.syrjala@linux.intel.com
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由 Ville Syrjälä 提交于
Pass the drm_device to drm_helper_mode_fill_fb_struct() so that we can populate fb->dev early. Will make it easier to use the fb before we register it. @@ identifier fb, mode_cmd; @@ void drm_helper_mode_fill_fb_struct( + struct drm_device *dev, struct drm_framebuffer *fb, const struct drm_mode_fb_cmd2 *mode_cmd ); @@ identifier fb, mode_cmd; @@ void drm_helper_mode_fill_fb_struct( + struct drm_device *dev, struct drm_framebuffer *fb, const struct drm_mode_fb_cmd2 *mode_cmd ) { ... } @@ function func; identifier dev; expression E1, E2; @@ func(struct drm_device *dev, ...) { ... drm_helper_mode_fill_fb_struct( + dev, E1, E2); ... } @@ expression E1, E2; @@ drm_helper_mode_fill_fb_struct( + dev, E1, E2); v2: Rerun spatch due to code changes Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481748539-18283-1-git-send-email-ville.syrjala@linux.intel.com
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由 Jan Kara 提交于
Every single user of vmf->virtual_address typed that entry to unsigned long before doing anything with it so the type of virtual_address does not really provide us any additional safety. Just use masked vmf->address which already has the appropriate type. Link: http://lkml.kernel.org/r/1479460644-25076-3-git-send-email-jack@suse.czSigned-off-by: NJan Kara <jack@suse.cz> Acked-by: NKirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Ross Zwisler <ross.zwisler@linux.intel.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 29 11月, 2016 13 次提交
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由 Jordan Crouse 提交于
Most 5XX targets have GPMU (Graphics Power Management Unit) that handles a lot of the heavy lifting for power management including thermal and limits management and dynamic power collapse. While the GPMU itself is optional, it is usually nessesary to hit aggressive power targets. The GPMU firmware needs to be loaded into the GPMU at init time via a shared hardware block of registers. Using the GPU to write the microcode is more efficient than using the CPU so at first load create an indirect buffer that can be executed during subsequent initalization sequences. After loading the GPMU gets initalized through a shared register interface and then we mostly get out of its way and let it do its thing. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Jordan Crouse 提交于
Add support for the A5XX family of Adreno GPUs. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Jordan Crouse 提交于
Disable the interrupt during the init sequence to avoid having interrupts fired for errors and other things that we are not ready to handle while initializing. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Jordan Crouse 提交于
The adreno code inherited a silly workaround from downstream from the bad old days before decent clock control. grp_clk[0] (named 'src_clk') doesn't actually exist - it was used as a proxy for whatever the core clock actually was (usually 'core_clk'). All targets should be able to correctly request 'core_clk' and get the right thing back so zap the anachronism and directly use grp_clk[0] to control the clock rate. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Jordan Crouse 提交于
Add helper functions for TYPE4 and TYPE7 ME opcodes that replace TYPE0 and TYPE3 starting with the A5XX targets. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Jordan Crouse 提交于
Add a new generic function to write a "64" bit value. This isn't actually a 64 bit operation, it just writes the upper and lower 32 bit of a 64 bit value to a specified LO and HI register. If a particular target doesn't support one of the registers it can mark that register as SKIP and writes/reads from that register will be quietly dropped. This can be immediately put in place for the ringbuffer base and the RPTR address. Both writes are converted to use adreno_gpu_write64() with their respective high and low registers and the high register appropriately marked as SKIP for both 32 bit targets (a3xx and a4xx). When a5xx comes it will define valid target registers for the 'hi' option and everything else will just work. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Jordan Crouse 提交于
Add some new functions to manipulate GPU registers. gpu_read64 and gpu_write64 can read/write a 64 bit value to two 32 bit registers. For 4XX and older these are normally perfcounter registers, but future targets will use 64 bit addressing so there will be many more spots where a 64 bit read and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Jordan Crouse 提交于
When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Jordan Crouse 提交于
There are very few register accesses in the common code. Cut down the list of common registers to just those that are used. This saves const space and saves us the effort of maintaining registers for A3XX and A4XX that don't exist or are unused. Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
Pull in a5xx registers. Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
Scratch registers move, annoyingly enough, in a5xx. Move to per-generation aNxx_recover() fxn. Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
For backwards compat, the rd format puts the high 32b after the size field in the GPUADDR packet. Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
For a5xx the gpu is 64b so we need to change iova to 64b everywhere. On the display side, iova is still 32b so it can ignore the upper bits. (Although all the armv8 devices have an iommu that can map 64b pa to 32b iova.) Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 28 11月, 2016 8 次提交
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由 Rob Clark 提交于
Previous value really only made sense on armv7 without LPAE. Everything that supports more than 4g of memory also has iommu's that can map anything. Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Archit Taneja 提交于
In add_components_mdp, we parse the endpoints in MDP output ports using the helper for_each_endpoint_of_node(). Our function calls of_node_put() on the endpoint node before we iterate over the next one. This is already done by the helper, and results in trying to decrement the refcount twice. Remove the extra of_node_put calls. This fixes warnings seen when we try to insert the driver as a module on IFC6410. Reported-by: NIlia Mirkin <imirkin@alum.mit.edu> Signed-off-by: NArchit Taneja <architt@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
The mode_config->max_{width,height} is for the maximum size of a fb, not the max scanout limits (of the layer-mixer). It is legal, and in fact common, to create a larger fb, only only scan-out a smaller part of it. For example multi-monitor configurations for x11, or android wallpaper layer (which is created larger than the screen resolution for fast scrolling by just changing the src x/y coordinates). Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
If the dumpstate modparam is enabled, for debugging error irq's, also dump SMP state. Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
Previously, SMP block allocation was not checked in the plane's atomic_check() fxn, so we could fail allocation SMP block allocation at atomic_update() time. Re-work the block allocation to request blocks during atomic_check(), but not update the hw until committing the atomic update. Since SMP blocks allocated at atomic_check() time, we need to manage the SMP state as part of mdp5_state (global atomic state). This actually ends up significantly simplifying the SMP management, as the SMP module does not need to manage the intermediate state between assigning new blocks before setting flush bits and releasing old blocks after vblank. (The SMP registers and SMP allocation is not double-buffered, so newly allocated blocks need to be updated in kms->prepare_commit() released blocks in kms->complete_commit().) Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
(re)assign the hw pipes to planes based on required caps, and to handle situations where we could not modify an in-use plane (ie. SMP block reallocation). This means all planes advertise the superset of formats and properties. Userspace must (as always) use atomic TEST_ONLY step for atomic updates, as not all planes may be available for use on every frame. The mapping of hwpipe to plane is stored in mdp5_state, so that state updates are atomically committed in the same way that plane/etc state updates are managed. This is needed because the mdp5_plane_state keeps a pointer to the hwpipe, and we don't want global state to become out of sync with the plane state if an atomic update fails, we hit deadlock/ backoff scenario, etc. The use of state_lock keeps multiple parallel updates which both re-assign hwpipes properly serialized. Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
Add basic state duplication/apply mechanism. Following commits will move actual global hw state into this. The state_lock allows multiple concurrent updates to proceed as long as they don't both try to alter global state. The ww_mutex mechanism will trigger backoff in case of deadlock between multiple threads trying to update state. Signed-off-by: NRob Clark <robdclark@gmail.com> Reviewed-by: NArchit Taneja <architt@codeaurora.org>
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