1. 27 2月, 2010 3 次提交
  2. 02 2月, 2010 1 次提交
    • M
      MIPS: Alchemy: Fix dbdma ring destruction memory debugcheck. · 22f4bb68
      Manuel Lauss 提交于
      DBDMA descriptors need to be located at 32-byte aligned addresses;
      however kmalloc in conjunction with the SLAB allocator and
      CONFIG_DEBUG_SLUB enabled doesn't deliver any.  The dbdma code works
      around that by allocating a larger area and realigning the start
      address within it.
      
      When freeing a channel however this adjustment is not taken into
      account which results in an oops:
      
      Kernel bug detected[#1]:
      [...]
      Call Trace:
      [<80186010>] cache_free_debugcheck+0x284/0x318
      [<801869d8>] kfree+0xe8/0x2a0
      [<8010b31c>] au1xxx_dbdma_chan_free+0x2c/0x7c
      [<80388dc8>] au1x_pcm_dbdma_free+0x34/0x4c
      [<80388fa8>] au1xpsc_pcm_close+0x28/0x38
      [<80383cb8>] soc_codec_close+0x14c/0x1cc
      [<8036dbb4>] snd_pcm_release_substream+0x60/0xac
      [<8036dc40>] snd_pcm_release+0x40/0xa0
      [<8018c7a8>] __fput+0x11c/0x228
      [<80188f60>] filp_close+0x7c/0x98
      [<80189018>] sys_close+0x9c/0xe4
      [<801022a0>] stack_done+0x20/0x3c
      
      Fix this by recording the address delivered by kmalloc() and using
      it as parameter to kfree().
      
      This fix is only necessary with the SLAB allocator and CONFIG_DEBUG_SLAB
      enabled;  non-debug SLAB, SLUB do return nicely aligned addresses,
      debug-enabled SLUB currently panics early in the boot process.
      Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
      To: Linux-MIPS <linux-mips@linux-mips.org>
      Cc: Manuel Lauss <manuel.lauss@gmail.com>
      Patchwork: http://patchwork.linux-mips.org/patch/878/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      22f4bb68
  3. 13 1月, 2010 1 次提交
  4. 02 11月, 2009 2 次提交
  5. 01 10月, 2009 1 次提交
  6. 24 9月, 2009 1 次提交
    • R
      cpumask: remove dangerous CPU_MASK_ALL_PTR, &CPU_MASK_ALL.: mips · 51c870a2
      Rusty Russell 提交于
      (Thanks to Al Viro for reminding me of this, via Ingo)
      
      CPU_MASK_ALL is the (deprecated) "all bits set" cpumask, defined as so:
      
      	#define CPU_MASK_ALL (cpumask_t) { { ... } }
      
      Taking the address of such a temporary is questionable at best,
      unfortunately 321a8e9d (cpumask: add CPU_MASK_ALL_PTR macro) added
      CPU_MASK_ALL_PTR:
      
      	#define CPU_MASK_ALL_PTR (&CPU_MASK_ALL)
      
      Which formalizes this practice.  One day gcc could bite us over this
      usage (though we seem to have gotten away with it so far).
      
      So replace everywhere which used &CPU_MASK_ALL or CPU_MASK_ALL_PTR
      with the modern "cpu_all_mask" (a real struct cpumask *), and remove
      CPU_MASK_ALL_PTR altogether.
      Signed-off-by: NRusty Russell <rusty@rustcorp.com.au>
      Acked-by: NIngo Molnar <mingo@elte.hu>
      Reported-by: NAl Viro <viro@zeniv.linux.org.uk>
      Cc: Mike Travis <travis@sgi.com>
      51c870a2
  7. 18 9月, 2009 2 次提交
  8. 04 8月, 2009 1 次提交
  9. 17 6月, 2009 4 次提交
    • M
      MIPS: Alchemy: devboards: Convert to gpio calls. · ce65cc8f
      Manuel Lauss 提交于
      Replace a few open-coded GPIO register accesses with gpio calls.
      Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      ce65cc8f
    • M
      MIPS: Alchemy: xxs1500: use linux gpio api. · b6c9f105
      Manuel Lauss 提交于
      Replace a few GPIO register accesses in the board init code with calls to
      the gpio api.
      Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      b6c9f105
    • M
      MIPS: Alchemy: MTX-1: Use linux gpio api. · bb706b28
      Manuel Lauss 提交于
      Replace a few GPIO register accesses in the board init code with calls
      to the gpio api.
      Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      bb706b28
    • M
      MIPS: Alchemy: Rewrite GPIO support. · 51e02b02
      Manuel Lauss 提交于
      The current in-kernel Alchemy GPIO support is far too inflexible for
      all my use cases.  To address this, the following changes are made:
      
      * create generic functions which deal with manipulating the on-chip
        GPIO1/2 blocks.  Such functions are universally useful.
      * Macros for GPIO2 shared interrupt management and block control.
      * support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros.
      
        If CONFIG_GPIOLIB is not enabled, provide linux gpio framework
        compatibility by directly inlining the GPIO1/2 functions.  GPIO access
        is limited to on-chip ones and they can be accessed as documented in
        the datasheets (GPIO0-31 and 200-215).
      
        If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and
        one for GPIO2, are registered.  GPIOs can still be accessed by using
        the numberspace established in the databooks.
      
        However this is not yet flexible enough for my uses:  My Alchemy
        systems have a documented "external" gpio interface (fixed, different
        numberspace) and can support a variety of baseboards, some of which
        are equipped with I2C gpio expanders.  I want to be able to provide
        the default 16 GPIOs of the CPU board numbered as 0..15 and also
        support gpio expanders, if present, starting as gpio16.
      
        To achieve this, a new Kconfig symbol for Alchemy is introduced,
        CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal
        that they don't want the Alchemy numberspace exposed to the outside
        world, but instead want to provide their own.  Boards are now respon-
        sible for providing the linux gpio interface glue code (either in a
        custom gpio.h header (in board include directory) or with gpio_chips).
      
        To make the board-specific inlined gpio functions work, the MIPS
        Makefile must be changed so that the mach-au1x00/gpio.h header is
        included _after_ the board headers, by moving the inclusion of
        the mach-au1x00/ to the end of the header list.
      
        See arch/mips/include/asm/mach-au1x00/gpio.h for more info.
      Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
      Acked-by: NFlorian Fainelli <florian@openwrt.org>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      51e02b02
  10. 14 5月, 2009 1 次提交
  11. 07 4月, 2009 1 次提交
  12. 30 3月, 2009 3 次提交
  13. 28 2月, 2009 1 次提交
  14. 31 1月, 2009 1 次提交
  15. 11 1月, 2009 13 次提交
  16. 28 10月, 2008 1 次提交
  17. 11 10月, 2008 1 次提交