1. 16 9月, 2011 1 次提交
  2. 11 8月, 2011 2 次提交
    • R
      bna: ENET and Tx Rx Redesign Enablement · 078086f3
      Rasesh Mody 提交于
      Change details:
      This patch contains additional structure and function definition changes
      that are required to enable the new msgq/enet/txrx redesign introduced
      by the previous 4 patches.
       - structure and function definition changes to header files as a result
         of Ethport, Enet, IOCEth, Tx, Rx redesign.
       - ethtool changes to use new enet function and definitions
       - Set number of Tx and Rx queues bassed on underlying hardware. Define
         separate macros for maximum and supported numbers of Tx and Rx queues
         based on underlying hardware. Take VLAN header into account for MTU
         calculation. Default to INTx mode when pci_enable_msix() fails. Set a
         bit in Rx poll routine, check and wait for that bit to be cleared in
         the cleanup routine before proceeding.
       - The TX and Rx coalesce settings are programmed in steps of 5 us. The value
         that are not divisible by 5 are rounded to the next lower number. This was
         causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
         When creating Rx and Tx object, we are currently assigning the default
         values of Rx and Tx coalescing_timeo. If these values are changed in the
         driver to a different value, the change is lost during such operations as
         MTU change. In order to avoid that, pass the configured value of
         coalescing_timeo before Rx and Tx object creation. Fix
         bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
       - Reorg uninitialization path in case of pci_probe failure.
       - Hardware clock setup changes to pass asic generation, port modes and
         asic mode as part firmware boot parameters to firmware.
       - FW mailbox interface changes to defined asic specific mailbox interfaces.
         h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
         up mailbox definitions and usage for new and old HW. Eliminated usage of
         ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
         host offsets for CPE/RME queue registers.
       - Implement polling mechanism for FW ready to have poll mechanism replaces
         the current interrupt based FW READY method. The timer based poll routine
         in IOC will query the ioc_fwstate register to see if there is a state
         change in FW, and sends the READY event. Removed infrastructure needed to
         support mbox READY event from fw as well as IOC code.
       - Move FW init to HW init. Handle the case where PCI mapping goes away when
         IOCPF state machine is waiting for semaphore.
       - Add IOC mbox call back to client indicating that the command is sent.
      Signed-off-by: NRasesh Mody <rmody@brocade.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      078086f3
    • J
      bna: Move the Brocade driver · f844a0ea
      Jeff Kirsher 提交于
      Moves the Brocade driver into drivers/net/ethernet/brocade/ and make
      the necessary Kconfig and Makefile changes.
      
      CC: Rasesh Mody <rmody@brocade.com>
      CC: Debashis Dutt <ddutt@brocade.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      f844a0ea
  3. 23 7月, 2011 2 次提交
  4. 26 12月, 2010 1 次提交
  5. 24 8月, 2010 1 次提交