1. 26 12月, 2017 22 次提交
  2. 07 12月, 2017 1 次提交
  3. 06 12月, 2017 2 次提交
  4. 03 12月, 2017 1 次提交
  5. 01 12月, 2017 2 次提交
  6. 29 11月, 2017 5 次提交
  7. 28 11月, 2017 4 次提交
    • A
      ARM: dts: logicpd-som-lv: Fix gpmc addresses for NAND and enet · 3c18bbf3
      Adam Ford 提交于
      This patch fixes and issue where the NAND and GPMC based ethernet
      controller stopped working.  This also updates the GPMC settings
      to be consistent with the Logic PD Torpedo development from the
      commit listed above.
      
      Fixes: 44e47164 ("ARM: dts: omap3: Fix NAND device nodes")
      Signed-off-by: NAdam Ford <aford173@gmail.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      3c18bbf3
    • T
      ARM: dts: Fix omap4 hang with GPS connected to USB by using wakeupgen · cf87634c
      Tony Lindgren 提交于
      There's been a reproducable USB OHCI/EHCI cpuidle related hang on omap4
      for a while that happens after about 20 - 40 minutes on an idle system
      with some data feeding device being connected, like a USB GPS device or
      a cellular modem.
      
      This issue happens in cpuidle states C2 and C3 and does not happen if
      cpuidle is limited to C1 state only. The symptoms are that the whole
      system hangs and never wakes up from idle, and if a watchdog is
      configured the system reboots after a while.
      
      Turns out that OHCI/EHCI devices on omap4 are trying to use the GIC
      interrupt controller directly as a parent instead of the WUGEN. We
      need to pass the interrupts through WUGEN to GIC to provide the wakeup
      events for the processor.
      
      Let's fix the issue by removing the gic interrupt-parent and use the
      default interrupt-parent wakeupgen instead. Note that omap5.dtsi had
      this already fixes earlier by commit 7136d457 ("ARM: omap: convert
      wakeupgen to stacked domains") but we somehow missed omap4 at that
      point.
      
      Fixes: 7136d457 ("ARM: omap: convert wakeupgen to stacked domains")
      Cc: Dave Gerlach <d-gerlach@ti.com>
      Cc: Nishanth Menon <nm@ti.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
      Reviewed-by: NRoger Quadros <rogerq@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      cf87634c
    • F
      ARM: dts: NSP: Fix PPI interrupt types · 5f1aa51c
      Florian Fainelli 提交于
      Booting a kernel results in the kernel warning us about the following
      PPI interrupts configuration:
      [    0.105127] smp: Bringing up secondary CPUs ...
      [    0.110545] GIC: PPI11 is secure or misconfigured
      [    0.110551] GIC: PPI13 is secure or misconfigured
      
      Fix this by using the appropriate edge configuration for PPI11 and
      PPI13, this is similar to what was fixed for Northstar (BCM5301X) in
      commit 0e34079c ("ARM: dts: BCM5301X: Correct GIC_PPI interrupt
      flags").
      
      Fixes: 7b2e987d ("ARM: NSP: add minimal Northstar Plus device tree")
      Fixes: 1a9d53ca ("ARM: dts: NSP: Add TWD Support to DT")
      Acked-by: NJon Mason <jon.mason@broadcom.com>
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      5f1aa51c
    • F
      ARM: dts: NSP: Disable AHCI controller for HR NSP boards · 77416ab3
      Florian Fainelli 提交于
      The AHCI controller is currently enabled for all of these boards:
      bcm958623hr and bcm958625hr would result in a hard hang on boot that we
      cannot get rid of. Since this does not appear to have an easy and simple
      fix, just disable the AHCI controller for now until this gets resolved.
      
      Fixes: 70725d6e ("ARM: dts: NSP: Enable SATA on bcm958625hr")
      Fixes: d454c376 ("ARM: dts: NSP: Add new DT file for bcm958623hr")
      Acked-by: NJon Mason <jon.mason@broadcom.com>
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      77416ab3
  8. 20 11月, 2017 1 次提交
    • A
      ARM: dts: r8a779x: Add '#reset-cells' in cpg-mssr · 098f5305
      Arnd Bergmann 提交于
      With the latest dtc, we get many warnings about the missing
      '#reset-cells' property in these controllers, e.g.:
      
      arch/arm/boot/dts/r8a7790-lager.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /can@e6e80000:resets[0])
      arch/arm/boot/dts/r8a7792-blanche.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/dma-controller@e6700000:resets[0])
      arch/arm/boot/dts/r8a7792-wheat.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/ethernet@e6800000:resets[0])
      arch/arm/boot/dts/r8a7793-gose.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /gpio@e6050000:resets[0])
      arch/arm/boot/dts/r8a7794-alt.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /i2c@e6500000:resets[0])
      arch/arm/boot/dts/r8a7794-silk.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /interrupt-controller@e61c0000:resets[0])
      
      This adds it for the three r8a779x chips that were lacking it. The
      binding mandates this as <1>, so this is the value I use.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      [geert: Add fix for r8a7793.dtsi]
      Fixes: 34fbd2b1 ("ARM: dts: r8a7790: Add reset control properties")
      Fixes: 6e11a322 ("ARM: dts: r8a7792: Add reset control properties")
      Fixes: 84fb19e1 ("ARM: dts: r8a7793: Add reset control properties")
      Fixes: 615beb75 ("ARM: dts: r8a7794: Add reset control properties")
      Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
      Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      098f5305
  9. 16 11月, 2017 1 次提交
  10. 11 11月, 2017 1 次提交