提交 03163470 编写于 作者: F Fabio Estevam 提交者: Shawn Guo

ARM: dts: imx6sx-sdb: Add PCIe support

Add support for PCIe support.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>
上级 f92717f6
......@@ -118,6 +118,17 @@
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};
reg_pcie_gpio: regulator-pcie-gpio {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_reg>;
regulator-name = "MPCIE_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
......@@ -199,6 +210,14 @@
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie_gpio>;
status = "okay";
};
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
......@@ -440,6 +459,18 @@
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
>;
};
pinctrl_pcie_reg: pciereggrp {
fsl,pins = <
MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
>;
};
pinctrl_peri_3v3: peri3v3grp {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
......
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