We need to add "clean-files" in Makfiles to clean up DT blobs, but we
often miss to do so.

Since there are no source files that end with .dtb or .dtb.S, so we
can clean-up those files from the top-level Makefile.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NRob Herring <robh@kernel.org>

LS1088A contains eight ARM v8 CortexA53 processor cores
with 32 KB L1-D cache and 32 KB L1-I cache

Features summary
 Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
  - Arranged as two clusters of four cores sharing a 1 MB L2 cache
  - Speed Up to 1.5 GHz
  - Support for cluster power-gating.
 Cache coherent interconnect (CCI-400)
  - Hardware-managed data coherency
  - Up to 700 MHz
 One 64-bit DDR4 SDRAM memory controller with ECC
 Data path acceleration architecture 2.0 (DPAA2)
 Three PCIe 3.0 controllers
 One serial ATA (SATA 3.0) controller
 Three high-speed USB 3.0 controllers with integrated PHY

 Following levels of DTSI/DTS files have been created for the LS1088A
  SoC family:

         - fsl-ls1088a.dtsi:
                 DTS-Include file for NXP LS1088A SoC.

         - fsl-ls1088a-qds.dts:
                 DTS file for NXP LS1088A QDS board.

         - fsl-ls1088a-rdb.dts:
                 DTS file for NXP LS1088A RDB board
Signed-off-by: NHarninder Rai <harninder.rai@nxp.com>
Signed-off-by: NAshish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>`
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This patch adds the device tree support for FSL LS2088A SoC based on
ARMv8 architecture.

Following levels of DTSI/DTS files have been created for the LS2088A
SoC family:

     - fsl-ls2088a.dtsi:
            DTS-Include file for FSL LS2088A SoC.

     - fsl-ls2088a-qds.dts:
            DTS file for FSL LS2088A QDS board.

     - fsl-ls2088a-rdb.dts:
            DTS file for FSL LS2088A RDB board.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: NAshish Kumar <ashish.kumar@nxp.com>
Signed-off-by: NAbhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

LS1012A features an advanced 64-bit ARM v8 CortexA53 processor
with 32 KB of parity protected L1-I cache, 32 KB of ECC protected
L1-D cache, as well as 256 KB of ECC protected L2 cache.

Features summary
 One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
  - Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC
    protection
  - Speed up to 800 MHz
  - Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
  - Neon SIMD engine
  - ARM v8 cryptography extensions
 One 16-bit DDR3L SDRAM memory controller
 ARM core-link CCI-400 cache coherent interconnect
 Cryptography acceleration (SEC)
 One Configurable x3 SerDes
 One PCI Express Gen2 controller, supporting x1 operation
 One serial ATA (SATA Gen 3.0) controller
 One USB 3.0/2.0 controller with integrated PHY

 Following levels of DTSI/DTS files have been created for the LS1012A
   SoC family:

           - fsl-ls1012a.dtsi:
                   DTS-Include file for FSL LS1012A SoC.

           - fsl-ls1012a-frdm.dts:
                   DTS file for FSL LS1012A FRDM board.

           - fsl-ls1012a-qds.dts:
                   DTS file for FSL LS1012A QDS board.

           - fsl-ls1012a-rdb.dts:
                    DTS file for FSL LS1012A RDB board.
Signed-off-by: NHarninder Rai <harninder.rai@nxp.com>
Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The LS1046A QorIQ development system (QDS) board is a high-performance
computing, evaluation, development, and test platform supporting the
LS1046A SoC.
Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The LS1046A reference design board (RDB) is a high-performance computing,
evaluation, and development platform that supports the LS1046A SoC.
Signed-off-by: NMingkai Hu <Mingkai.Hu@nxp.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The LS1043a-QDS board is a high-performance computing, evaluation,
development, and test platform supporting the LS1043a SoC.

shawn.guo: sort the entries in Makefile alphabetcially
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NWenbin Song <Wenbin.Song@freescale.com>
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds build support for LS2080a QDS & RDB board DTS files
in the arm64 DTS Makefile.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Freescale is renaming the LS2085A SoC to LS2080A. This patch
addresses the same.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Freescale will be a spinning-out a set of ARMv8 based SoCs which
will be based on a similar overall SoC architecture. So, this patch
converts the existing infrastructure in the arm64/dts, arm64/Kconfig
and arm64/configs to use the generic convention ARCH_LAYERSCAPE
in place of the more specific FSL_LS2085A, to save code duplication
later-on.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch adds the device tree support for FSL LS2085A SoC
based on ARMv8 architecture.

Following levels of DTSI/DTS files have been created for the
LS2085A SoC family:

- fsl-ls2085a.dtsi:
DTS-Include file for FSL LS2085A SoC.

- fsl-ls2085a-simu.dts:
DTS file for FSL LS2085a software simulator model.

In addition, this patch adds build support for FSL's LS2085A
simulator model in arm64 dts Makefile.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NArnab Basu <arnab_basu@rocketmail.com>
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add initial device tree nodes for exynos7 SoC and board dts file
to support espresso board based on exynos7 SoC.
Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Tested-by: NThomas Abraham <thomas.ab@samsung.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Initial revision of device tree for AMD Seattle Development platform.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Signed-off-by: NThomas Lendacky <Thomas.Lendacky@amd.com>
Signed-off-by: NJoel Schopp <Joel.Schopp@amd.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Moving dts files to vendor subdirs.
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRobert Richter <rrichter@cavium.com>