- 27 2月, 2010 4 次提交
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由 David Daney 提交于
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/892/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David Daney 提交于
The userspace runtime linker uses the elf_platform to find the libraries optimized for the current CPU archecture variant. First we need to allow it to be set to something other than NULL. Follow-on patches will set some values for specific CPUs. GLIBC already does the right thing. The kernel just needs to supply good data. Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/891/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Roel Kluin 提交于
Signed-off-by: NRoel Kluin <roel.kluin@gmail.com> To: linux-mips@linux-mips.org To: Andrew Morton <akpm@linux-foundation.org> To: LKML <linux-kernel@vger.kernel.org> Patchwork: http://patchwork.linux-mips.org/patch/860/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David Daney 提交于
For processors that have more than 64 TLBs, we need to decode both config1 and config4 to determine the total number TLBs. Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/866/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 11 2月, 2010 1 次提交
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由 David Daney 提交于
The patch that adds cpu_probe_vmbits is erroneously writing to reserved bit 12. Since we are really only probing high bits, don't write this bit with a one. Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Guenter Roeck <guenter.roeck@ericsson.com> Patchwork: http://patchwork.linux-mips.org/patch/949/Acked-by: NGuenter Roeck <guenter.roeck@ericsson.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 03 2月, 2010 1 次提交
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由 Guenter Roeck 提交于
Linux kernel 2.6.32 and later allocate address space from the top of the kernel virtual memory address space. This patch implements virtual memory size detection for 64 bit MIPS CPUs to avoid resulting crashes. Signed-off-by: NGuenter Roeck <guenter.roeck@ericsson.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/935/Reviewed-by: NDavid Daney <ddaney@caviumnetworks.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 17 12月, 2009 1 次提交
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由 Wu Zhangjin 提交于
Loongson 2F supports CPU clock scaling. When put it into wait mode by setting the frequency as ZERO it will stay in this mode until an external interrupt wakes the CPU again. To enable clock scaling support, an external timer of a known stable rate is required. Signed-off-by: NWu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: cpufreq@vger.kernel.org, Cc: Dave Jones <davej@redhat.com>, Cc: Dominik Brodowski <linux@dominikbrodowski.net>, Cc: yanh@lemote.com Cc: huhb@lemote.com, Patchwork: http://patchwork.linux-mips.org/patch/660/ Patchwork: http://patchwork.linux-mips.org/patch/751/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 02 11月, 2009 1 次提交
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由 Chris Dearman 提交于
Signed-off-by: NChris Dearman <chris@mips.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 18 9月, 2009 3 次提交
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由 Maxime Bizon 提交于
Todo: Nothing ever detects CPU_BCM6338 but the code tests for it anyway. Signed-off-by: NMaxime Bizon <mbizon@freebox.fr> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Manuel Lauss 提交于
Eliminate the 'allow_au1k_wait' variable. MIPS kernel installs the Alchemy-specific wait code before timer initialization; if the C0 timer must be used for timekeeping the wait function is set to NULL which means no wait implementation is available. As a sideeffect, the 'wait instruction available' output in /proc/cpuinfo now correctly indicates whether 'wait' is usable. Run-tested on DB1200. Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 25 6月, 2009 1 次提交
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由 Ralf Baechle 提交于
Some of the were relying into smp.h being dragged in by another header which of course is fragile. <asm/cpu-info.h> uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 30 3月, 2009 1 次提交
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由 Manuel Lauss 提交于
This patch removes the various CPU_AU1??? model constants in favor of a single CPU_ALCHEMY one. All currently existing Alchemy models are identical in terms of cpu core and cache size/organization. The parts of the mips kernel which need to know the exact CPU revision extract it from the c0_prid register already; and finally nothing else in-tree depends on those any more. Should a new variant with slightly different "company options" and/or "processor revision" bits in c0_prid appear, it will be supported immediately (minus an exact model string in cpuinfo). Signed-off-by: NManuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 12 3月, 2009 1 次提交
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由 Shinya Kuribayashi 提交于
Current VR5500 processor support lacks of some functions which are expected to be configured/synthesized on arch initialization. Here're some VR5500A spec notes: * All execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 11 1月, 2009 2 次提交
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由 Manuel Lauss 提交于
Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent device. As a nice side effect, this also enables use of the 'wait' instruction for runtime idle power savings. If the counters aren't enabled/working properly, fall back on the cp0 counter clock code. Signed-off-by: NManuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David Daney 提交于
Add OCTEON constants to asm/cpu.h and asm/module.h. Add probe function for Cavium OCTEON CPUs and hook it up. Signed-off-by: NTomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 30 10月, 2008 2 次提交
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由 Ralf Baechle 提交于
As noticed by David Daney <ddaney@caviumnetworks.com>, the old long switch statement did not comply with the Linux C coding style. It was also yet another place of code to be changed when adding a new processor type leading to annoying bugs for example in /proc/cpuinfo. Fixed by moving the setting of the CPU type string into the core of the probing code and a few BUG_ON() test to ensure the CPU probing code indeed did its job and removing multiple now redundant tests. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Acked-by: NDavid Daney <ddaney@caviumnetworks.com>
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- 11 10月, 2008 1 次提交
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由 David Daney 提交于
Probe for watch register characteristics, and report them in /proc/cpuinfo. Signed-off-by: NDavid Daney <ddaney@avtrex.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 04 10月, 2008 1 次提交
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由 Kevin D. Kissell 提交于
Rework of SMTC support to make it work with the new clock event system, allowing "tickless" operation, and to make it compatible with the use of the "wait_irqoff" idle loop. The new clocking scheme means that the previously optional IPI instant replay mechanism is now required, and has been made more robust. Signed-off-by: NKevin D. Kissell <kevink@paralogos.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 21 9月, 2008 1 次提交
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由 Atsushi Nemoto 提交于
If an interrupt happened between checking of NEED_RESCHED and WAIT instruction, adjust EPC to restart from checking of NEED_RESCHED. Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 29 4月, 2008 3 次提交
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由 Daniel Laird 提交于
Signed-off-by: Ndaniel.j.laird <daniel.j.laird@nxp.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NChris Dearman <chris@mips.com> Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Chris Dearman 提交于
Signed-off-by: NChris Dearman <chris@mips.com> Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 12 3月, 2008 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 29 1月, 2008 1 次提交
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由 Manuel Lauss 提交于
This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: NManuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 16 11月, 2007 1 次提交
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由 Ralf Baechle 提交于
Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 12 10月, 2007 4 次提交
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由 Franck Bui-Huu 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Aurelien Jarno 提交于
Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 15 9月, 2007 1 次提交
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由 Ralf Baechle 提交于
Another issue with 20Kc's WAIT, waiting for more details. With the 2.6.23 release immindent simply disable the use of WAIT instead of a more fancy workaround. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 21 7月, 2007 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 11 7月, 2007 3 次提交
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由 Marc St-Jean 提交于
Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: NMarc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Fuxin Zhang 提交于
Signed-off-by: NFuxin Zhang <zhangfx@lemote.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 06 7月, 2007 1 次提交
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由 Ralf Baechle 提交于
The idle loop goes to sleep using the WAIT instruction if !need_resched(). This has is suffering from from a race condition that if if just after need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but we've just completed the test so go to sleep anyway. This would be trivial to fix by just disabling interrupts during that sequence as in: local_irq_disable(); if (!need_resched()) __asm__("wait"); local_irq_enable(); but the processor architecture leaves it undefined if a processor calling WAIT with interrupts disabled will ever restart its pipeline and indeed some processors have made use of the freedom provided by the architecture definition. This has been resolved and the Config7.WII bit indicates that the use of WAIT is safe on 24K, 24KE and 34K cores. It also is safe on 74K starting revision 2.1.0 so enable the use of WAIT with interrupts disabled for 74K based on a c0_prid of at least that. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 27 6月, 2007 1 次提交
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由 Ralf Baechle 提交于
We used to avoid the WAIT entirely on the 20K but really only need to do this on early revs of the 20K. Without this a 20K was a bit of a power hog. Well, in the lower power power hog category ;-) Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 20 2月, 2007 1 次提交
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由 Atsushi Nemoto 提交于
This fixes some sparse warnings. ("warning: symbol 'foo' was not declared. Should it be static?") Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 19 2月, 2007 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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