1. 16 10月, 2008 11 次提交
  2. 12 10月, 2008 1 次提交
    • I
      warnings: fix arch/x86/kernel/io_apic_64.c · d562353a
      Ingo Molnar 提交于
      fix:
      
       arch/x86/kernel/io_apic_64.c: In function ‘print_local_APIC’:
       arch/x86/kernel/io_apic_64.c:1284: warning: format ‘%08x’ expects type ‘unsigned int’, but argument 2 has type ‘long unsigned int’
       arch/x86/kernel/io_apic_64.c:1285: warning: format ‘%08x’ expects type ‘unsigned int’, but argument 2 has type ‘long unsigned int’
      
      We want to print the two halves of 'icr' at 32 bit width.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      d562353a
  3. 11 8月, 2008 1 次提交
  4. 24 7月, 2008 1 次提交
    • M
      x86: PIC, L-APIC and I/O APIC debug information · 32f71aff
      Maciej W. Rozycki 提交于
       Dump all the PIC, local APIC and I/O APIC information at the
      fs_initcall() level, which is after ACPI (if used) has initialised PCI
      information, making the point of invocation consistent across MP-table and
      ACPI platforms.  Remove explicit calls to print_IO_APIC() from elsewhere.
      Make the interface of all the functions involved consistent between 32-bit
      and 64-bit versions and make them all static by default by the means of a
      New-and-Improved(TM) __apicdebuginit() macro.
      
       Note that like print_IO_APIC() all these only output anything if
      "apic=debug" has been passed to the kernel through the command line.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Cc: Chuck Ebbert <cebbert@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      32f71aff
  5. 19 7月, 2008 1 次提交
  6. 18 7月, 2008 2 次提交
    • M
      x86: I/O APIC: Always report how the timer has been set up · 49a66a0b
      Maciej W. Rozycki 提交于
      Following recent (and less so) issues with the 8254 timer when routed
      through the I/O or local APIC, always report which configurations have
      been tried and which one has been set up eventually.  This is so that logs
      posted by people for some other reason can be used as a cross-reference
      when investigating any possible future problems.
      
      The change unifies messages printed on 32-bit and 64-bit platforms and
      adds trailing newlines (removes leading ones), so that proper log level
      annotation can be used and any possible interspersed output will not cause
      a mess.
      
      I have chosen to use apic_printk(APIC_QUIET, ...) rather than printk(...)
      so that the distinction of these messages is maintained making possible
      future decisions about changes in this area easier.  A change posted
      separately making apic_verbosity unsigned removes any extra code that
      would otherwise be generated as a result of this design decision.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      49a66a0b
    • M
      x86: I/O APIC: Include <asm/i8259.h> required by some code · 17c44697
      Maciej W. Rozycki 提交于
      Include <asm/i8259.h> for i8259A_lock used in print_PIC() -- #if-0-ed out
      by default.  The 32-bit version gets it right already.
      
      The plan is to enable this code with "apic=debug" eventually.  This will
      aid with debugging strange problems without the need to ask people to
      apply patches.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      17c44697
  7. 13 7月, 2008 1 次提交
  8. 12 7月, 2008 7 次提交
    • Y
      x86: make read_apic_id return final apicid · 4c9961d5
      Yinghai Lu 提交于
      also remove GET_APIC_ID when read_apic_id is used.
      
      need to apply after
      	[PATCH] x86: mach_apicdef.h need to include before smp.h
      Signed-off-by: NYinghai Lu <yhlu.kernel@gmail.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      4c9961d5
    • S
      x64, x2apic/intr-remap: MSI and MSI-X support for interrupt remapping infrastructure · 75c46fa6
      Suresh Siddha 提交于
      MSI and MSI-X support for interrupt remapping infrastructure.
      
      MSI address register will be programmed with interrupt-remapping table
      entry(IRTE) index and the IRTE will contain information about the vector,
      cpu destination, etc.
      
      For MSI-X, all the IRTE's will be consecutively allocated in the table,
      and the address registers will contain the starting index to the block
      and the data register will contain the subindex with in that block.
      
      This also introduces a new irq_chip for cleaner irq migration (in the process
      context as opposed to the current irq migration in the context of an interrupt.
      interrupt-remapping infrastructure will help us achieve this).
      
      As MSI is edge triggered, irq migration is a simple atomic update(of vector
      and cpu destination) of IRTE and flushing the hardware cache.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      75c46fa6
    • S
      x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping · 89027d35
      Suresh Siddha 提交于
      IO-APIC support in the presence of interrupt-remapping infrastructure.
      
      IO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)
      index and the IRTE will contain information about the vector, cpu destination,
      trigger mode etc, which traditionally was present in the IO-APIC RTE.
      
      Introduce a new irq_chip for cleaner irq migration (in the process
      context as opposed to the current irq migration in the context of an interrupt.
      interrupt-remapping infrastructure will help us achieve this cleanly).
      
      For edge triggered, irq migration is a simple atomic update(of vector
      and cpu destination) of IRTE and flush the hardware cache.
      
      For level triggered, we need to modify the io-apic RTE aswell with the update
      vector information, along with modifying IRTE with vector and cpu destination.
      So irq migration for level triggered is little  bit more complex compared to
      edge triggered migration. But the good news is, we use the same algorithm
      for level triggered migration as we have today, only difference being,
      we now initiate the irq migration from process context instead of the
      interrupt context.
      
      In future, when we do a directed EOI (combined with cpu EOI broadcast
      suppression) to the IO-APIC, level triggered irq migration will also be
      as simple as edge triggered migration and we can do the irq migration
      with a simple atomic update to IO-APIC RTE.
      
      TBD: some tests/changes needed in the presence of fixup_irqs() for
      level triggered irq migration.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      89027d35
    • S
      x64, x2apic/intr-remap: basic apic ops support · 1b374e4d
      Suresh Siddha 提交于
      Introduce basic apic operations which handle the apic programming. This
      will be used later to introduce another specific operations for x2apic.
      
      For the perfomance critial accesses like IPI's, EOI etc, we use the
      native operations as they are already referenced by different
      indirections like genapic, irq_chip etc.
      
      64bit Paravirt ops can also define their apic operations accordingly.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      1b374e4d
    • S
      x64, x2apic/intr-remap: ioapic routines which deal with initial io-apic RTE setup · 4dc2f96c
      Suresh Siddha 提交于
      Generic ioapic specific routines which be used later during enabling
      interrupt-remapping.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      4dc2f96c
    • M
      x86: I/O APIC: Never configure IRQ2 · af174783
      Maciej W. Rozycki 提交于
      There is no such entity as ISA IRQ2.  The ACPI spec does not make it
      explicitly clear, but does not preclude it either -- all it says is ISA
      legacy interrupts are identity mapped by default (subject to overrides),
      but it does not state whether IRQ2 exists or not.  As a result if there is
      no IRQ0 override, then IRQ2 is normally initialised as an ISA interrupt,
      which implies an edge-triggered line, which is unmasked by default as this
      is what we do for edge-triggered I/O APIC interrupts so as not to miss an
      edge.
      
      To the best of my knowledge it is useless, as IRQ2 has not been in use
      since the PC/AT as back then it was taken by the 8259A cascade interrupt
      to the slave, with the line position in the slot rerouted to newly-created
      IRQ9.  No device could thus make use of this line with the pair of 8259A
      chips.  Now in theory INTIN2 of the I/O APIC may be usable, but the
      interrupt of the device wired to it would not be available in the PIC mode
      at all, so I seriously doubt if anybody decided to reuse it for a regular
      device.
      
      However there are two common uses of INTIN2.  One is for IRQ0, with an
      ACPI interrupt override (or its equivalent in the MP table).  But in this
      case IRQ2 is gone entirely with INTIN0 left vacant.  The other one is for
      an 8959A ExtINTA cascade.  In this case IRQ0 goes to INTIN0 and if ACPI is
      used INTIN2 is assumed to be IRQ2 (there is no override and ACPI has no
      way to report ExtINTA interrupts).  This is where a problem happens.
      
      The problem is INTIN2 is configured as a native APIC interrupt, with a
      vector assigned and the mask cleared.  And the line may indeed get active
      and inject interrupts if the master 8959A has its timer interrupt enabled
      (it might happen for other interrupts too, but they are normally masked in
      the process of rerouting them to the I/O APIC).  There are two cases where
      it will happen:
      
      * When the I/O APIC NMI watchdog is enabled.  This is actually a misnomer
        as the watchdog pulses are delivered through the 8259A to the LINT0
        inputs of all the local APICs in the system.  The implication is the
        output of the master 8259A goes high and low repeatedly, signalling
        interrupts to INTIN2 which is enabled too!
      
        [The origin of the name is I think for a brief period during the
        development we had a capability in our code to configure the watchdog to
        use an I/O APIC input; that would be INTIN2 in this scenario.]
      
      * When the native route of IRQ0 via INTIN0 fails for whatever reason -- as
        it happens with the system considered here.  In this scenario the timer
        pulse is delivered through the 8259A to LINT0 input of the local APIC of
        the bootstrap processor, quite similarly to how is done for the watchdog
        described above.  The result is, again, INTIN2 receives these pulses
        too.  Rafael's system used to escape this scenario, because an incorrect
        IRQ0 override would occupy INTIN2 and prevent it from being unmasked.
      
      My conclusion is IRQ2 should be excluded from configuration in all the
      cases and the current exception for ACPI systems should be lifted.  The
      reason being the exception not only being useless, but harmful as well.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
      Cc: Matthew Garrett <mjg59@srcf.ucam.org>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      af174783
    • M
      x86: L-APIC: Always fully configure IRQ0 · c88ac1df
      Maciej W. Rozycki 提交于
      Unlike the 32-bit one, the 64-bit variation of the LVT0 setup code for
      the "8259A Virtual Wire" through the local APIC timer configuration does
      not fully configure the relevant irq_chip structure.  Instead it relies on
      the preceding I/O APIC code to have set it up, which does not happen if
      the I/O APIC variants have not been tried.
      
      The patch includes corresponding changes to the 32-bit variation too
      which make them both the same, barring a small syntactic difference
      involving sequence of functions in the source.  That should work as an aid
      with the upcoming merge.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
      Cc: Matthew Garrett <mjg59@srcf.ucam.org>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c88ac1df
  9. 10 7月, 2008 3 次提交
  10. 09 7月, 2008 1 次提交
    • R
      x86: fix C1E && nx6325 stability problem · e2079c43
      Rafael J. Wysocki 提交于
      The problems are that, with the ACPI vs timer overring issue _fixed_,
      after using the box for some time (between several seconds and 1 hour, at
      random) processes get very high CPU loads (once I've got X using 107% of
      the CPU, for example) and the system becomes unresponsive, as though there
      were interrupts lost or something similar.
      
      Andreas Herrman reproduced similar problems:
      
      > Ok, now I've reproduced the stability problem.
      > - Using tip/master,
      > - reverting e38502eb8aa82314d5ab0eba45f50e6790dadd88 and
      > - applying your patch from this posting
      >   http://marc.info/?l=linux-kernel&m=121539354224562&w=4
      >
      > Starting X, firefox, gimp, tuxpaint and doing some drawing in tuxpaint
      > results in a slow system. Drawing is almost not possible anymore --
      > Selections of new colors, cursors etc. is performed with huge delay
      > if it's performed at all.
      >
      > BTW, the code sets up timer IRQ as Virtual Wire IRQ:
      >
      > Jul  8 14:57:58 kodscha IO-APIC (apicid-pin) 2-22, 2-23 not connected.
      > Jul  8 14:57:58 kodscha ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
      > Jul  8 14:57:58 kodscha ...trying to set up timer as Virtual Wire IRQ... works.
      >
      > and both INT0 and INT2 of IOAPIC are masked:
      >
      > Jul  8 14:57:58 kodscha NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:
      > Jul  8 14:57:58 kodscha 00 000 1    0    0   0   0    0    0    00
      > Jul  8 14:57:58 kodscha 01 003 0    0    0   0   0    1    1    31
      > Jul  8 14:57:58 kodscha 02 003 1    0    0   0   0    0    0    30
      >
      > I've also seen strange CPU utilization -- with syslog-ng:
      >
      > top - 15:33:06 up 35 min,  4 users,  load average: 1.70, 0.68, 0.37
      > Tasks:  64 total,   4 running,  60 sleeping,   0 stopped,   0 zombie
      > Cpu0  :  0.0%us,100.0%sy,  0.0%ni,  0.0%id,  0.0%wa,  0.0%hi,  0.0%si,  0.0%st
      > Cpu1  :  6.4%us, 87.2%sy,  0.0%ni,  5.8%id,  0.0%wa,  0.6%hi,  0.0%si,  0.0%st
      > Mem:    895384k total,   283568k used,   611816k free,    35492k buffers
      > Swap:  1959920k total,        0k used,  1959920k free,   163044k cached
      >
      >   PID USER      PR  NI  VIRT  RES  SHR S %CPU %MEM    TIME+  COMMAND
      >  4632 root      20   0 17216  800  580 S  104  0.1   0:34.22 syslog-ng
      > 28505 root      20   0  205m  11m 4024 S    6  1.3   0:21.16 X
      > 28518 root      20   0 56292 5652 4492 S    1  0.6   0:01.80 fluxbox
      >     1 root      20   0  3724  608  508 S    0  0.1   0:00.36 init
      >
      > So far I have no clue why C1E-idle in conjunction with virtual wire
      > mode causes this strange behaviour.
      >
      > ... and I start to think about the root cause of all this.
      >
      > I've performed similar tests under X with the IRQ0/INT0 configuration and
      > I did not see above symptoms.
      
      So lets fall back to the IRQ0/INT0 configuration on this box.
      
      This basically restores the dont-use-the-lapic-timer exception mechanism
      that was unconditional on this box prior commit 8750bf5 ("x86: add C1E
      aware idle function").
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      e2079c43
  11. 08 7月, 2008 11 次提交
    • C
      x86: nmi_watchdog - use NMI_NONE by default · c376d454
      Cyrill Gorcunov 提交于
      There is no need to keep NMI_DISABLED definition and use it
      for nmi_watchdog by default. Here is the point why:
      
      - IO-APIC and APIC chips are programmed for nmi_watchdog support at very
        early stage of kernel booting and not having nmi_watchdog specified as
        boot option lead only to nmi_watchdog becomes to NMI_NONE anyway
      - enable nmi_watchdog thru /proc/sys/kernel/nmi if it was not specified at
        boot is not possible too (even having this sysfs entry)
      Signed-off-by: NCyrill Gorcunov <gorcunov@gmail.com>
      Cc: macro@linux-mips.org
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c376d454
    • G
      x86: change __setup_vector_irq with setup_vector_irq · 3fde6900
      Glauber Costa 提交于
      We create a version of it for i386, and then take the CONFIG_X86_64
      ifdef out of the game. We could create a __setup_vector_irq for i386,
      but it would incur in an unnecessary lock taking. Moreover, it is better
      practice to only export setup_vector_irq anyway.
      Signed-off-by: NGlauber Costa <gcosta@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3fde6900
    • M
      x86: fix IO APIC breakage on HP nx6325, v2 · 7f0dbbc0
      Maciej W. Rozycki 提交于
      > That helped a lot, the system seems to work normally now.
      >
      > Here's the relevant snippet from dmesg:
      >
      > [    0.108006] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
      > [    0.108006] ..MP-BIOS bug: 8254 timer not connected to IO-APIC
      > [    0.108006] ...trying to set up timer (IRQ0) through the 8259A ... <3>
      > [    0.108006] ..... (found apic 0 pin 2) ...<3> failed.
      > [    0.108006] ...trying to set up timer as Virtual Wire IRQ...<3> works.
      >
      > and the whole thing is at: http://www.sisk.pl/kernel/debug/20080618/dmesg-2.log
      
       Hmm, that only proved the 8259A is indeed wired to the pin #2 of the I/O
      APIC.
      
      > I, personally, don't have any and AMD only has SB600 documentation on its
      > web page (it's still marked as "AMD confidential" ;-)).
      
       Well, the IC block is most likely the same as that's not rocket science
      and once done there is no need to fiddle with that.  That written, I am
      afraid there is nothing useful about the IC in the document, except that
      it's there and consists of an I/O APIC providing 24 inputs and the usual
      pair of 8259A cores.  Thanks for the reference anyway.
      
      > There is an interrupt controller in there, but I'm not sure if there's any
      > 8259A.  The northbridge is on the CPU, actually.
      
       I will praise the day someone ships an x86 machine without an 8259A core!
      
       As expressed in another mail I suspect there may actually be a direct
      route from the 8254 to INTIN0 in the southbridge -- this is what other
      bootstrap logs seen in the Internet suggest.  This would mean this
      particular BIOS is buggy (is it the latest version?) and provides an
      incorrect IRQ override in its ACPI tables, for example because the
      responsible block has been blindly copied from a machine using a commoner
      wiring.  This could be moderately easily fixed up with a quirk based on
      the PCI ID (after checking it again, we actually used to have a quirk for
      ATI in this area, but the way it was done suggests the issue was not
      understood well enough).
      
       Could you please remove the hack sent yesterday and test the patch
      provided below?  I do hope it builds, but I have no immediate means to
      check it.  Please report the output.  The intent is to test INTIN0
      directly before testing INTIN2 through the 8259A.  Thanks.
      
       Aside of that, what I have gathered from your reports (please correct me
      if I have got it wrong) is that when the through-8259A mode is used, then
      after a while 8254 timer interrupts stop arriving.  What's interesting,
      the "Virtual Wire IRQ" seems to work for you correctly (that's quite an
      odd setup where a local APIC input is used in the native mode -- please
      post /proc/interrupts for confirmation), which in turn implies the master
      8259A drives its INT output as we expect.  Why would the I/O APIC input
      have problems then?  Hmm...
      
      [ mingo@elte.hu: revert the "x86: fix IO APIC breakage on HP nx6325"
        version. ]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      7f0dbbc0
    • M
      x86: fix IO APIC breakage on HP nx6325 · cd08d075
      Maciej W. Rozycki 提交于
      On Thu, 19 Jun 2008, Rafael J. Wysocki wrote:
      
      > >  With such a configuration the "x86: I/O APIC: timer through 8259A
      > > second-chance" patch should not matter, because the only change it
      > > introduces is an attempt to try the same I/O APIC pin again, but with the
      > > IRQ0 line of the master 8259A enabled.  That's not a terribly unusual
      > > configuration and nothing should get confused in the system.
      >
      > But it _does_ get confused, really.
      
       Something certainly gets confused, but so far I am not sure which bit
      exactly it is, are you?
      
      > >  Barring the unlikely possibility of the 8259A actually being wired to
      > > INTIN2 of the I/O APIC I can see two possible explanations:
      > >
      > > 1. The 8259A interrupt actually escapes to the CPU somehow and is handled
      > >    as an ExtINTA interrupt.  This would make the code in check_timer()
      > >    decide it has found a working configuration, while actually it has been
      > >    fooled.
      [...]
      > Here you go:
      >
      > [    0.108006] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
      > [    0.108006] ..MP-BIOS bug: 8254 timer not connected to IO-APIC
      > [    0.108006] ...trying to set up timer (IRQ0) through the 8259A ... <3>
      > [    0.108006] ..... (found apic 0 pin 2) ...<3> works.
      >
      > The full dmesg is at: http://www.sisk.pl/kernel/debug/20080618/dmesg-1.log
      
      Thanks.  In this case I suspect the case #1 quoted above happens, that is
      the 8259A manages to deliver its interrupt somehow.  Note at this stage it
      is meant to be in the AEOI mode, so it can happily resubmit the interrupt
      indefinitely with no additional handling as long as it receives INTA
      cycles.
      
      Can you please try the patch below on top of "x86: I/O APIC: timer
      through 8259A second-chance" to see whether my hypothesis is true?  It
      modifies the through-8259A setup path so that the APIC input gets masked,
      but the 8259A has the timer interrupt still enabled.  Let me know how the
      timer interrupt is routed in this case.
      Bisected-by: N"Rafael J. Wysocki" <rjw@sisk.pl>
      Tested-by: N"Rafael J. Wysocki" <rjw@sisk.pl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      cd08d075
    • C
      x86, io-apic: use predefined names instead of numeric constants · 46b3b4ef
      Cyrill Gorcunov 提交于
      This patch replaces some hard-coded numbers with predefined names.
      Signed-off-by: NCyrill Gorcunov <gorcunov@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      46b3b4ef
    • C
      x86: IO-APIC - use NMI_NONE instead of numeric constant · 067fa0ff
      Cyrill Gorcunov 提交于
      Not sure but maybe it is better to use NMI_DISABLED,
      will take a look. But for now this patch is not change
      anything in logic so it will not hurt/broke the kernel.
      For most cases nmi_watchdog assignment is by one of NMI_*
      macro so I think there it make sense too.
      Signed-off-by: NCyrill Gorcunov <gorcunov@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      067fa0ff
    • I
      x86 build fix: · b1b57ee1
      Ingo Molnar 提交于
        arch/x86/kernel/io_apic_64.c: In function 'check_timer':
        arch/x86/kernel/io_apic_64.c:1688: error: 'vector' undeclared (first use in this function)
        arch/x86/kernel/io_apic_64.c:1688: error: (Each undeclared identifier is reported only once
        arch/x86/kernel/io_apic_64.c:1688: error: for each function it appears in.)
      b1b57ee1
    • T
      x86: make irq_cfg static · 7223daf5
      Thomas Gleixner 提交于
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      7223daf5
    • M
      x86: I/O APIC: timer through 8259A second-chance · 691874fa
      Maciej W. Rozycki 提交于
      Some systems incorrectly report the ExtINTA pin of the I/O APIC as the
      genuine target of the timer interrupt.  Here is a change that copies timer
      pin information found to the other pin if one has been found only.  This
      way both a direct and a through-8259A route is tested with the pin letting
      these problematic systems work well enough.  If no timer pin information
      has been found for the I/O APIC, then local APIC variations are tried
      only, similarly to what is done without the change (except without the
      misleading messages).
      
      Obviously if we try the first-chance path without being told by the BIOS
      to do so, we should not complain either, so do not print the message in
      this case.
      
      The 64-bit variation should be updated with a call to
      replace_pin_at_irq() which can be done with the upcoming merge.  Since
      add_pin_to_irq() is now always called in the first-chance path, the
      condition to require it in the second-chance path no longer happens.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      691874fa
    • M
      x86: I/O APIC: keep the timer IRQ masked during set-up · 03be7505
      Maciej W. Rozycki 提交于
      Keep the timer interrupt line masked when reconfiguring its interrupt
      redirection entry in the I/O APIC.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      03be7505
    • M
      x86: I/O APIC: unmask the second-chance timer interrupt · 24742ece
      Maciej W. Rozycki 提交于
      Unmask the timer interrupt line set up in the through-8259A mode
      explicitly after setup_timer_IRQ0_pin() has set up the I/O APIC interrupt
      redirection entry to let the two operations be unbound from each other.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      24742ece