The DSI controllers are powered by a (typically 1.2V) regulator. Usually
this is always on, so there was no need to support enabling or disabling
it thus far. But in order not to consume any power when DSI is inactive,
give the driver a chance to enable or disable the supply as needed.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Revert commit 18ebc0f4 "drm/tegra: hdmi: Enable VDD earlier for
hotplug/DDC" and instead add a new supply for the +5V pin on the HDMI
connector.

The vdd-supply property refers to the regulator that supplies the
AVDD_HDMI input on Tegra, rather than the +5V HDMI connector pin. This
was never a problem before, because all boards had that pin hooked up to
a regulator that was always on. Starting with Dalmore and continuing
with Venice2, the +5V pin is controllable via a GPIO. For reasons
unknown, the GPIO ended up as the controlling GPIO of the AVDD_HDMI
supply in the Dalmore and Venice2 DTS files. But that's not correct.
Instead, a separate supply must be introduced so that the +5V pin can be
controlled separately from the supplies that feed the HDMI block within
Tegra.

A new hdmi-supply property is introduced that takes the place of the
vdd-supply and vdd-supply is only enabled when HDMI is enabled rather
than all the time.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for eDP functionality found on Tegra124 and later SoCs. Only
fast link training is currently supported.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The head number of a given display controller is fixed in hardware and
required to program outputs appropriately. Relying on the driver probe
order to determine this number will not work, since that could yield a
situation where the second head was probed first and would be assigned
head number 0 instead of 1.

By explicitly specifying the head number in the device tree, it is no
longer necessary to rely on these assumptions. As a fallback, if the
property isn't available, derive the head number from the display
controller node's position in the device tree. That's somewhat more
reliable than the previous default but not a proper solution.
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This commit adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features like ganged
mode won't work.

Due to the lack of other test hardware, some sections of the driver are
hardcoded to work with Dalmore.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The display controller primary clock was recently renamed to "dc", so
update the example to reflect that.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use the DRM panel framework to attach a panel to an output. If the panel
attached to a connector supports supports the backlight brightness
accessors, a property will be available to allow the brightness to be
modified from userspace.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Update all the Tegra DT bindings to require resets/reset-names properties
where the HW module has reset inputs. Remove any entries from clocks or
clock-names that were only required to identify reset inputs, rather than
referring to real clocks.

This is a DT-ABI-incompatible change. It is the first of two changes
required for me to consider the Tegra DT bindings as stable, the other
being conversion to the common DMA DT bindings.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-By: NTerje Bergstrom <tbergstrom@nvidia.com>

Many of the Tegra DT binding documents say nothing about the clocks or
clock-names properties, yet those are present and required in DT files.
This patch simply updates the documentation file to match the implicit
definition of the binding, based on real-world DT content.

All Tegra bindings that mention clocks are updated to have consistent
wording and formatting of the clock-related properties.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-By: NTerje Bergstrom <tbergstrom@nvidia.com>

This commit adds a KMS driver for the Tegra20 SoC. This includes basic
support for host1x and the two display controllers found on the Tegra20
SoC. Each display controller can drive a separate RGB/LVDS output.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NMark Zhang <markz@nvidia.com>
Reviewed-by: NMark Zhang <markz@nvidia.com>
Tested-by: NMark Zhang <markz@nvidia.com>
Tested-and-acked-by: NAlexandre Courbot <acourbot@nvidia.com>
Acked-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Tested-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>