Add a clock for video input subsystem (EXIV) on
UniPhier LD11/LD20 SoCs.
Signed-off-by: NKatsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add clock for audio subsystem (AIO) and SoC internal audio codec
(EVEA) on UniPhier LD11/LD20 SoCs.
Signed-off-by: NKatsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch enables clocks for STM32H743 boards.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>

for MFD changes:
Acked-by: NLee Jones <lee.jones@linaro.org>

for DT-Bindings
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch exposes clk_gate_ops::is_enabled as functions
that can be directly called and assigned in places like this so
we don't need wrapper functions that do nothing besides forward
the call.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Suggested-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We need to export clk_gate_is_enabled() from clk framework, then
to avoid compilation issue we have to rename clk_gate_is_enabled()
in NXP LPC32xx clock driver.
We changed all gate op with 'lpc32xx_' prefix:
lpc32xx_clk_gate_enable(),
lpc32xx_clk_gate_disable(),
lpc32xx_clk_gate_is_enabled().
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NVladimir Zapolskiy <vz@mleia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add basic clock data for Socionext's new SoC PXs3.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The old code uses tcxo (19.2MHz) as watchdog clock but actually the
watchdog uses 32K clock, as result the watchdog timeout cannot be set
correctly and delay long time to reset SoC.

So this patch is to use 'ref32k' as clock source for watchdog.

Fixes: 72ea4861 ("clk: hi6220: Clock driver support for Hisilicon hi6220 SoC")
Signed-off-by: NLeo Yan <leo.yan@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The RK808 and RK805 PMICs are using a similar register map.
We can reuse the clk driver for the RK805 PMIC. So let's add
the RK805 in the Kconfig description.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NJoseph Chen <chenjh@rock-chips.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds the common function to reset the clk rate in order to
be able to use it in other cases.
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: NHiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com>
Acked-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This propagates rate requests from the display interface to the divider
or PLL output, allowing to hit the required display rate in many more
cases.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Tested-By: NWladimir J. van der Laan <laanwj@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull more Allwinner clock changes from Maxime Ripard:

 * Conversion of the last two SoCs (A10, A20) to the sunxi-ng framework

* tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: Add sun4i/sun7i CCU driver
  dt-bindings: List devicetree binding for the CCU of Allwinner A10
  dt-bindings: List devicetree binding for the CCU of Allwinner A20

gcc-8 reports an uninitialized variable access in a code path
that we would see with incorrect DTB input:

drivers/clk/sunxi/clk-sun8i-bus-gates.c: In function 'sun8i_h3_bus_gates_init':
drivers/clk/sunxi/clk-sun8i-bus-gates.c:85:27: error: 'clk_parent' may be used uninitialized in this function [-Werror=maybe-uninitialized]

This works around by skipping invalid input and printing a warning
instead if it ever happens. The problem was apparently part of the
initiali driver submission, but older compilers don't notice it.

Fixes: ab6e23a4 ("clk: sunxi: Add H3 clocks support")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Make this const as it is only stored in the const field of a
clk_init_data structure.
Signed-off-by: NBhumika Goyal <bhumirks@gmail.com>
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

HSDK board manages its clocks using various PLLs. These PLL have same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.

Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.

We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.

As of today we add support for PLLs that generate clock for the
HSDK arc cpus, system, ddr, AXI tunnel and hdmi.

By this patch we add support for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: NVineet Gupta <vgupta@synopsys.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

clk_div_table are not supposed to change at runtime. All functions
working with clk_div_table provided by <linux/clk-provider.h> work
with const clk_div_table. So mark the non-const structs as const.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

clk_div_table are not supposed to change at runtime. All functions
working with clk_div_table provided by <linux/clk-provider.h> work
with const clk_div_table. So mark the non-const structs as const.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add clock control for ethernet controller on Pro4, PXs2, LD11 and LD20.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This bit is pin control, and needs to be carefully managed by the
new pin control driver.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

clk_ops are not supposed to change at runtime. All functions
working with clk_ops provided by <linux/clk-provider.h> work
with const clk_ops. So mark the non-const clk_ops as const.

Here, Function "clk_reg_prcc" is used to initialized clk_init_data.
clk_init_data is working with const clk_ops. So make clk_reg_prcc
non-const clk_ops argument as const.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

clk_ops are not supposed to change at runtime. All functions
working with clk_ops provided by <linux/clk-provider.h> work
with const clk_ops. So mark the non-const clk_ops as const.

Here, Function "clk_reg_sysctrl" is used to initialized clk_init_data.
clk_init_data is working with const clk_ops. So make clk_reg_sysctrl
non-const clk_ops argument as const.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

clk_ops are not supposed to change at runtime. All functions
working with clk_ops provided by <linux/clk-provider.h> work
with const clk_ops. So mark the non-const clk_ops as const.

Here, Function "clk_reg_prcmu" is used to initialized clk_init_data.
clk_init_data is working with const clk_ops. So make clk_reg_prcmu
non-const clk_ops argument as const.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Introduce a clock controller driver for sun4i A10 and sun7i A20
series SoCs.
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Allwinner A10 is now driven by sunxi-ng CCU driver.

Add devicetree binding for it.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Allwinner A20 is now driven by sunxi-ng CCU driver.

Add devicetree binding for it.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This patch adds missing LPASS smmu clks which are required by the audio driver.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

- Added necessary delays in PLLU enable sequence during initialization
- Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were
missing).
Signed-off-by: NAlex Frid <afrid@nvidia.com>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Increased Tegra210 UTMIPLL power on delay to 20us (spec maximum is 15us).
Also remove a few empty lines to make it more clear the ACTIVE_DLY_COUNT
and ENABLE_DLY_COUNT fields.
Signed-off-by: NAlex Frid <afrid@nvidia.com>
Reviewed-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NJon Mayo <jmayo@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Switched Tegra210 PLLRE registration to common PLL ops instead of special
PLLRE ops used on previous Tegra chips. The latter ops do not follow
chip specific PLL frequency table, and do not apply chip specific rate
calculation method.

Removed unnecessary default rate setting that duplicates h/w reset
state, and is overwritten by clock initialization, anyway.
Signed-off-by: NAlex Frid <afrid@nvidia.com>
Reviewed-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NJon Mayo <jmayo@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Remove from Tegra210 PLLSS registration code sections that
- attempt to set PLL minimum rate (unnecessary, and dangerous if PLL
  is already enabled on boot)
- apply pre-Tegra210 defaults settings
- check IDDQ setting (duplicated with Tegra210 PLLSS check defaults)

Replaced setting of reference clock with check that default oscillator
selection is not changed, and failed registration otherwise as validation
was only done with the oscillator as the reference clock.

Reordered registration, so that PLL initialization is called after
VCOmin adjustment.
Signed-off-by: NAlex Frid <afrid@nvidia.com>
Reviewed-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Tegra210 PLLX uses the same sequences than then PLLC instances. So there
is no need to have a special registration function and ops struct for it.
Simplify the code by changing all references to the Tegra210 PLLX
registration function to the Tegra210 PLLC registration function and
avoid duplicate functionality.

Based on work by Alex Frid <afrid@nvidia.com>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

If the PLL is on, only warn if the defaults are not yet set. Otherwise be
silent.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NTimo Alho <talho@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Increase delay after PLL IDDQ release to 5us per PLL specifications.

based on work by Alex Frid <afrid@nvidia.com>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

I2C controllers are also on the APB bus and therefor need this flag to handle
resets correctly.
Signed-off-by: NAlex Frid <afrid@nvidia.com>
Reviewed-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Don't take the fractional part into account to calculate the effective
NDIV if fractional ndiv is not enabled.
Signed-off-by: NAlex Frid <afrid@nvidia.com>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Not all fields are read from the hw depending on the PLL type. Make sure
the other fields are 0 by clearing the structure beforehand to prevent
users such as the rate re-calculation code from using bogus values.

Based on work by  Alex Frid <afrid@nvidia.com>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

PLLD2 is used for HDMI which does not allow Spread Spectrum clocking.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Make sure the pll_ss ops are compiled even when only building for Tegra210.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NShreshtha Sahu <ssahu@nvidia.com>
Tested-by: NShreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: NJon Mayo <jmayo@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

PLL SS was only controlled when setting the PLL rate, not when the PLL itself
is enabled or disabled.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NJon Mayo <jmayo@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The clock bimc_gpu_clk_src is incorrectly set to use the shared rcg2
ops, which are for RCGs with child branches controlled by different
CPUs.

The result of the incorrect ops is that the GPU's PM runtime may leave
this clock set at a very low rate. Fix this issue by using the correct
rcg2 ops.

Fixes: a2e8272f ("clk: qcom: Add MSM8916 gpu clocks")
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>