clk: tegra: fix SS control on PLL enable/disable
PLL SS was only controlled when setting the PLL rate, not when the PLL itself is enabled or disabled. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: NJon Mayo <jmayo@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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