There is a cut and paste bug so we check "pclk" instead of "clk".
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Merge tag 'for_3.17/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung

Samsung clock patches for 3.17

1) non-critical fixes (without need to push to stable):

d5e136a2 clk: samsung: Register clk provider only after registering its all clocks
305cfab0 clk: samsung: Make of_device_id array const
e9d52956 clk: samsung: exynos5420: Setup clocks before system suspend
f65d5189 clk: samsung: trivial: Correct typo in author's name

2) Exynos CLKOUT driver:

800c9797 clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy
01f7ec26 clk: samsung: exynos4: Add CLKOUT clock hierarchy
1e832e51 clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
d19bb397 ARM: dts: exynos: Update PMU node with CLKOUT related data

3) Clock hierarchy extensions:

17d3f1d2 clk: exynos4: Add PPMU IP block source clocks.
ca5b4029 clk: samsung: register exynos5420 apll/kpll configuration data

4) ARM CLKDOWN functionality enablement for Exynos4 and 3250:

42773b28 clk: samsung: exynos4: Enable ARMCLK down feature
45c5b0a6 clk: samsung: exynos3250: Enable ARMCLK down feature

If the .debug_init op is provided, it will be called by
clk_debug_create_one(). If debug_init() returns an error code,
clk_debug_create_one() will return -ENOMEM, regardless of the
value returned from debug_init(). Tweak the code to return
the actual value returned by debug_init() instead.
Signed-off-by: NChris Brand <chris.brand@linaro.org>
Reviewed-by: NMatt Porter <mporter@linaro.org>
Reviewed-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds DT binding documentation for the Cirrus Logic
CLPS711X-based CPUs clock subsystem.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This adds the clock driver for Cirrus Logic CLPS711X series SoCs
using common clock infrastructure.
Designed primarily for migration CLPS711X subarch for multiplatform & DT,
for this as the "OF" and "non-OF" calls implemented.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch uses CLK_DIVIDER_ROUND_CLOSEST flag to specify
the divider has to round to closest div.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch extend the range of possible frequencies of the fs432c65
and fs660c32 Quad frequency synthesizers.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The patch added support for DT registration of ClockGenA9
It includes c32 type PLL.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NOlivier Bideau <olivier.bideau@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The patch added support for ClockGenD0/D2/D3
It includes one 660 Quadfs.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NOlivier Bideau <olivier.bideau@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The patch added support for DT registration of ClockGenC0
It includes 2 c32 type PLL and a 660 Quadfs.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NOlivier Bideau <olivier.bideau@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds the support of quadfs reset handling.
Signed-off-by: NOlivier Bideau <olivier.bideau@st.com>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch introduces polarity indication for pll power up bit
and for standby bit in order to have same code between stih416
and stih407 boards.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The patch added support for DT registration of ClockGenA0
It includes c32 type PLL.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NOlivier Bideau <olivier.bideau@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The patch supports the A9-mux clocks used by ClockGenA9
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NOlivier Bideau <olivier.bideau@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch is the Flexgen implementation reusing as much as possible
of Common Clock Framework functions.

The idea is to have an instance of "struct flexgen" per output clock.
It represents the clock cross bar (by a mux element), and the pre and final dividers
(using dividers and gates elements).
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NOlivier Bideau <olivier.bideau@st.com>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

A Flexgen structure is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

converts clkgen_pll_data tables into static const
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

converts stm_fs tables into static const
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Naming convention was changed in dts file but the
clock binding documentation hasn't been updated.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

There are some structs and arrays on the driver that are not used
anywhere else. Let's mark them as static.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This commit adds __iomem thoughout the sunxi clock driver, in places
where it was ommited. This cleans most of the sparse warnings we
are getting here.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch corrects mistyped author's name in four header files. While
at it, a copy/paste error in author's e-mail in one of the headers is
also fixed.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.

Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NAmit Daniel Kachhap <amit.daniel@samsung.com>
Tested-by: NArjun K.V <arjun.kv@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.

while at it, add these clks to save/restore list also.
Signed-off-by: NVikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Array of struct of_device_id may be be const as expected by
of_match_table field and of_find_matching_node_and_match() function.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Enable ARMCLK down feature on Exynos3250 SoC. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).

The feature behaves like very fast cpufreq ondemand governor.

The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).

The feature behaves like very fast cpufreq ondemand governor. In idle
mode this reduces energy consumption on full frequency chosen by
cpufreq governor by approximately:
 - Trats2:  6.5% (153 mA -> 143 mA)
 - Trats:  33.0% (180 mA -> 120 mA)
 - Gear1:  27.0% (180 mA -> 130 mA)

The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature and on Exynos4412 ARMCLK down is
enabled for all 4 cores.

Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and
Samsung Gear 1 (Exynos4212).
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: NDaniel Drake <drake@endlessm.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch extends nodes of PMU system controller on Exynos4210, 4x12,
5250 and 5420 SoCs with newly defined properties used by Exynos CLKOUT
driver.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch introduces a driver that handles configuration of CLKOUT pin
of Exynos SoCs that can be used to output certain clocks from inside of
the SoC to a dedicated output pin.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds definitions of clocks that are used to drive clock
output signals of particular CMU sub-blocks that are then fed to PMU and
handled by Exynos CLKOUT driver added in further patch.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next-sunxi

Allwinner clocks additions for 3.17

This pull request adds support for the clocks found in the newly supported
Allwinner A23 clocks.

This patch adds missing definitions of clocks from CPU and DMC clock
domains, which are necessary to properly represent CLKOUT clock hierarchy
added in further patch.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Merge tag 'qcom-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next-msm

qcom clock changes for 3.17

These patches add support for a handful of Qualcomm's SoC clock
controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064.
There's also a small collection of bug fixes that aren't critical
-rc worthy regressions because the consumer drivers aren't present
or using the buggy clocks and one optimization for HDMI.

This patch adds helper functions to configure clock parents and rates
as specified through 'assigned-clock-parents', 'assigned-clock-rates'
DT properties for a clock provider or clock consumer device.
The helpers are now being called by the bus code for the platform, I2C
and SPI busses, before the driver probing and also in the clock core
after registration of a clock provider.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The APQ8064 multimedia clock controller is fairly similar to the
8960 multimedia clock controller, except that gfx2d0/1 has been
removed and the gfx3d frequency is slightly faster when using the
newly introduced PLL15. We also add vcap clocks and a couple new
TV clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some SR type PLLs need to be configured for a certain rate when
linux boots. Add support for these types of PLLs so that we can
program PLL15's rate on apq8064.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the
child of the mdp_src clock. Fix it.

Fixes: 6d00b56f "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>