1. 28 10月, 2015 1 次提交
  2. 08 8月, 2015 1 次提交
    • S
      powerpc/fsl: Force coherent memory on e500mc derivatives · c6023202
      Scott Wood 提交于
      In CoreNet systems it is not allowed to mix M and non-M mappings to the
      same memory, and coherent DMA accesses are considered to be M mappings
      for this purpose.  Ignoring this has been observed to cause hard
      lockups in non-SMP kernels on e6500.
      
      Furthermore, e6500 implements the LRAT (logical to real address table)
      which allows KVM guests to control the WIMGE bits.  This means that
      KVM cannot force the M bit on the way it usually does, so the guest had
      better set it itself.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      c6023202
  3. 22 9月, 2014 1 次提交
  4. 11 6月, 2014 1 次提交
  5. 23 4月, 2014 3 次提交
  6. 20 3月, 2014 6 次提交
    • S
      powerpc/booke64: Critical and machine check exception support · 609af38f
      Scott Wood 提交于
      Add special state saving for critical and machine check exceptions.
      
      Most of this code could be used to handle debug exceptions taken from
      kernel space, but actually doing so is outside the scope of this patch.
      
      The various critical and machine check exceptions now point to their
      real handlers, rather than hanging the kernel.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      609af38f
    • S
      powerpc/booke64: Add crit/mc/debug support to EXCEPTION_COMMON · 31f71248
      Scott Wood 提交于
      Use the proper scratch SPRG and PACA region.  Introduce level-specific
      macros to simplify usage and avoid needing to do a bunch of token
      pasting throughout EXCEPTION_COMMON().
      
      Now that EXCEPTION_COMMON_DBG() is properly using the debug scratch
      register, there's no more need for the caller to move the value to the
      GEN scratch first.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      31f71248
    • S
      powerpc/booke64: Remove ints from EXCEPTION_COMMON · 28a3ded1
      Scott Wood 提交于
      The ints parameter was used to optionally insert RECONCILE_IRQ_STATE
      into EXCEPTION_COMMON.  However, since it came at the end of
      EXCEPTION_COMMON, there was no real benefit for it to be there as
      opposed to being called separately by the caller of EXCEPTION_COMMON.
      
      The ints parameter was causing some hassle when trying to add an extra
      macro layer.  Besides avoiding that, moving "ints" to the caller makes
      the code simpler by:
       - avoiding the asymmetry where INTS_RESTORE_HARD is called separately
      by the individual exception, but INTS_DISABLE was not
       - removing the no-op INTS_KEEP
       - not having an unnecessary macro parameter
      
      It also turned out to be necessary to delay the INTS_DISABLE
      in the case of special level exceptions until after we saved the
      old value of PACAIRQHAPPENED.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      28a3ded1
    • S
      powerpc/booke64: Use SPRG7 for VDSO · 9d378dfa
      Scott Wood 提交于
      Previously SPRG3 was marked for use by both VDSO and critical
      interrupts (though critical interrupts were not fully implemented).
      
      In commit 8b64a9df ("powerpc/booke64:
      Use SPRG0/3 scratch for bolted TLB miss & crit int"), Mihai Caraman
      made an attempt to resolve this conflict by restoring the VDSO value
      early in the critical interrupt, but this has some issues:
      
       - It's incompatible with EXCEPTION_COMMON which restores r13 from the
         by-then-overwritten scratch (this cost me some debugging time).
       - It forces critical exceptions to be a special case handled
         differently from even machine check and debug level exceptions.
       - It didn't occur to me that it was possible to make this work at all
         (by doing a final "ld r13, PACA_EXCRIT+EX_R13(r13)") until after
         I made (most of) this patch. :-)
      
      It might be worth investigating using a load rather than SPRG on return
      from all exceptions (except TLB misses where the scratch never leaves
      the SPRG) -- it could save a few cycles.  Until then, let's stick with
      SPRG for all exceptions.
      
      Since we cannot use SPRG4-7 for scratch without corrupting the state of
      a KVM guest, move VDSO to SPRG7 on book3e.  Since neither SPRG4-7 nor
      critical interrupts exist on book3s, SPRG3 is still used for VDSO
      there.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      Cc: Mihai Caraman <mihai.caraman@freescale.com>
      Cc: Anton Blanchard <anton@samba.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: kvm-ppc@vger.kernel.org
      9d378dfa
    • S
      powerpc/booke64: Fix exception numbers · c4787d1e
      Scott Wood 提交于
      altivec_unavailable was commented as 0xf20 but the code uses 0x200.
      Note that 0xf20 is also used by ap_unavailable.
      
      altivec_assist was commented as 0x1700 but the code uses 0x220.
      
      critical_input was commented as 0x580 but the code uses 0x100.
      
      machine_check was commented and implemented as 0x200, which conflicts
      with altivec_assist (it only builds because MC_EXCEPTION_PROLOG is
      commented out).  Changed to the fixed IVOR value of 0x000.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      c4787d1e
    • T
      powerpc/book3e: store crit/mc/dbg exception thread info · 19007b34
      Tiejun Chen 提交于
      We need to store thread info to these exception thread info like something
      we already did for PPC32.
      Signed-off-by: NTiejun Chen <tiejun.chen@windriver.com>
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      19007b34
  7. 11 1月, 2014 1 次提交
    • D
      powerpc: Replaced tlbilx with tlbwe in the initialization code · ed2ddc56
      Diana Craciun 提交于
      On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor
      state can execute TLB management instructions. If EPCR[DGTMI]=0
      tlbwe and tlbilx are allowed to execute normally in the guest state.
      
      A hypervisor may choose to virtualize TLB1 and for this purpose it
      may use IPROT to protect the entries for being invalidated by the
      guest. However, because tlbwe and tlbilx execution in the guest state
      are sharing the same bit, it is not possible to have a scenario where
      tlbwe is allowed to be executed in guest state and tlbilx traps. When
      guest TLB management instructions are allowed to be executed in guest
      state the guest cannot use tlbilx to invalidate TLB1 guest entries.
      
      Linux is using tlbilx in the boot code to invalidate the temporary
      entries it creates when initializing the MMU. The patch is replacing
      the usage of tlbilx in initialization code with tlbwe with VALID bit
      cleared.
      
      Linux is also using tlbilx in other contexts (like huge pages or
      indirect entries) but removing the tlbilx from the initialization code
      offers the possibility to have scenarios under hypervisor which are
      not using huge pages or indirect entries.
      Signed-off-by: NDiana Craciun <Diana.Craciun@freescale.com>
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      ed2ddc56
  8. 08 1月, 2014 1 次提交
  9. 17 10月, 2013 1 次提交
  10. 11 10月, 2013 1 次提交
  11. 14 8月, 2013 1 次提交
  12. 14 5月, 2013 1 次提交
    • S
      powerpc/booke64: Fix kernel hangs at kernel_dbg_exc · 6cecf76b
      Scott Wood 提交于
      MSR_DE is not cleared on entry to the kernel, and we don't clear it
      explicitly outside of debug code.  If we have MSR_DE set in
      prime_debug_regs(), and the new thread has events enabled in DBCR0
      (e.g.  ICMP is set in thread->dbsr0, even though it was cleared in the
      real DBCR0 when the thread got scheduled out), we'll end up taking a
      debug exception in the kernel when DBCR0 is loaded.  DSRR0 will not
      point to an exception vector, and the kernel ends up hanging at
      kernel_dbg_exc.  Fix this by always clearing MSR_DE when we load new
      debug state.
      
      Another observed source of kernel_dbg_exc hangs is with the branch
      taken event.  If this event is active, but we take a non-debug trap
      (e.g. a TLB miss or an asynchronous interrupt) before the next branch.
      We end up taking a branch-taken debug exception on the initial branch
      instruction of the exception vector, but because the debug exception is
      DBSR_BT rather than DBSR_IC we branch to kernel_dbg_exc before even
      checking the DSRR0 address.  Fix this by checking for DBSR_BT as well
      as DBSR_IC, which is what 32-bit does and what the comments suggest was
      intended in the 64-bit code as well.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      6cecf76b
  13. 13 3月, 2013 1 次提交
  14. 10 1月, 2013 1 次提交
  15. 13 9月, 2012 1 次提交
  16. 07 9月, 2012 1 次提交
  17. 05 9月, 2012 5 次提交
  18. 11 7月, 2012 1 次提交
  19. 10 7月, 2012 2 次提交
  20. 09 3月, 2012 4 次提交
    • B
      powerpc: Rework lazy-interrupt handling · 7230c564
      Benjamin Herrenschmidt 提交于
      The current implementation of lazy interrupts handling has some
      issues that this tries to address.
      
      We don't do the various workarounds we need to do when re-enabling
      interrupts in some cases such as when returning from an interrupt
      and thus we may still lose or get delayed decrementer or doorbell
      interrupts.
      
      The current scheme also makes it much harder to handle the external
      "edge" interrupts provided by some BookE processors when using the
      EPR facility (External Proxy) and the Freescale Hypervisor.
      
      Additionally, we tend to keep interrupts hard disabled in a number
      of cases, such as decrementer interrupts, external interrupts, or
      when a masked decrementer interrupt is pending. This is sub-optimal.
      
      This is an attempt at fixing it all in one go by reworking the way
      we do the lazy interrupt disabling from the ground up.
      
      The base idea is to replace the "hard_enabled" field with a
      "irq_happened" field in which we store a bit mask of what interrupt
      occurred while soft-disabled.
      
      When re-enabling, either via arch_local_irq_restore() or when returning
      from an interrupt, we can now decide what to do by testing bits in that
      field.
      
      We then implement replaying of the missed interrupts either by
      re-using the existing exception frame (in exception exit case) or via
      the creation of a new one from an assembly trampoline (in the
      arch_local_irq_enable case).
      
      This removes the need to play with the decrementer to try to create
      fake interrupts, among others.
      
      In addition, this adds a few refinements:
      
       - We no longer  hard disable decrementer interrupts that occur
      while soft-disabled. We now simply bump the decrementer back to max
      (on BookS) or leave it stopped (on BookE) and continue with hard interrupts
      enabled, which means that we'll potentially get better sample quality from
      performance monitor interrupts.
      
       - Timer, decrementer and doorbell interrupts now hard-enable
      shortly after removing the source of the interrupt, which means
      they no longer run entirely hard disabled. Again, this will improve
      perf sample quality.
      
       - On Book3E 64-bit, we now make the performance monitor interrupt
      act as an NMI like Book3S (the necessary C code for that to work
      appear to already be present in the FSL perf code, notably calling
      nmi_enter instead of irq_enter). (This also fixes a bug where BookE
      perfmon interrupts could clobber r14 ... oops)
      
       - We could make "masked" decrementer interrupts act as NMIs when doing
      timer-based perf sampling to improve the sample quality.
      
      Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      ---
      
      v2:
      
      - Add hard-enable to decrementer, timer and doorbells
      - Fix CR clobber in masked irq handling on BookE
      - Make embedded perf interrupt act as an NMI
      - Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
        to retrigger an interrupt without preventing hard-enable
      
      v3:
      
       - Fix or vs. ori bug on Book3E
       - Fix enabling of interrupts for some exceptions on Book3E
      
      v4:
      
       - Fix resend of doorbells on return from interrupt on Book3E
      
      v5:
      
       - Rebased on top of my latest series, which involves some significant
      rework of some aspects of the patch.
      
      v6:
       - 32-bit compile fix
       - more compile fixes with various .config combos
       - factor out the asm code to soft-disable interrupts
       - remove the C wrapper around preempt_schedule_irq
      
      v7:
       - Fix a bug with hard irq state tracking on native power7
      7230c564
    • B
      powerpc: Fix 64-bit BookE FP unavailable exceptions · 9424fabf
      Benjamin Herrenschmidt 提交于
      We were using CR0.EQ after EXCEPTION_COMMON, hoping it still
      contained whether we came from userspace or kernel space.
      
      However, under some circumstances, EXCEPTION_COMMON will
      call C code and clobber non-volatile registers, so we really
      need to re-load the previous MSR from the stackframe and
      re-test.
      
      While there, invert the condition to make the fast path more
      obvious and remove the BUG_OPCODE which was a debugging
      leftover and call .ret_from_except as we should.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      9424fabf
    • B
      powerpc: Disable interrupts in 64-bit kernel FP and vector faults · 9f2f79e3
      Benjamin Herrenschmidt 提交于
      If we get a floating point, altivec or vsx unavaible interrupt in
      kernel, we trigger a kernel error. There is no point preserving
      the interrupt state, in fact, that can even make debugging harder
      as the processor state might change (we may even preempt) between
      taking the exception and landing in a debugger.
      
      So just make those 3 disable interrupts unconditionally.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ---
      
      v2: On BookE only disable when hitting the kernel unavailable
          path, otherwise it will fail to restore softe as
          fast_exception_return doesn't do it.
      9f2f79e3
    • B
      powerpc: Call do_page_fault() with interrupts off · a546498f
      Benjamin Herrenschmidt 提交于
      We currently turn interrupts back to their previous state before
      calling do_page_fault(). This can be annoying when debugging as
      a bad fault will potentially have lost some processor state before
      getting into the debugger.
      
      We also end up calling some generic code with interrupts enabled
      such as notify_page_fault() with interrupts enabled, which could
      be unexpected.
      
      This changes our code to behave more like other architectures,
      and make the assembly entry code call into do_page_faults() with
      interrupts disabled. They are conditionally re-enabled from
      within do_page_fault() in the same spot x86 does it.
      
      While there, add the might_sleep() test in the case of a successful
      trylock of the mmap semaphore, again like x86.
      
      Also fix a bug in the existing assembly where r12 (_MSR) could get
      clobbered by C calls (the DTL accounting in the exception common
      macro and DISABLE_INTS) in some cases.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ---
      
      v2. Add the r12 clobber fix
      a546498f
  21. 29 6月, 2011 1 次提交
  22. 19 5月, 2011 2 次提交
  23. 06 5月, 2011 2 次提交