• M
    powerpc/booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int · 8b64a9df
    Mihai Caraman 提交于
    Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
    Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
    SPRG4-7 registers will be clobbered.
    For bolted TLB miss exception handlers, which is the version currently
    supported by KVM, use SPRN_SPRG_GEN_SCRATCH aka SPRG0 instead of
    SPRN_SPRG_TLB_SCRATCH aka SPRG6. Keep using TLB PACA slots to fit in one
    64-byte cache line.
    For critical exception handlers use SPRG3 instead of SPRG7. Provide a routine
    to store and restore user-visible SPRGs. This will be subsequently used
    to restore VDSO information in SPRG3. Add EX_R13 to paca slots to free up
    SPRG3 and change the critical exception epilog to use it.
    Signed-off-by: NMihai Caraman <mihai.caraman@freescale.com>
    Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
    8b64a9df
exceptions-64e.S 38.7 KB