1. 04 5月, 2012 2 次提交
  2. 02 5月, 2012 2 次提交
  3. 04 4月, 2012 1 次提交
  4. 20 3月, 2012 1 次提交
    • A
      ixgbe: Fix issues with SR-IOV loopback when flow control is disabled · 8f4a0a3d
      Alexander Duyck 提交于
      This patch allows us to avoid a Tx hang when SR-IOV is enabled.  This hang
      can be triggered by sending small packets at a rate that was triggering Rx
      missed errors from the adapter while the internal Tx switch and at least
      one VF are enabled.
      
      This was all due to the fact that under heavy stress the Rx FIFO never
      drained below the flow control high water mark.  This resulted in the Tx
      FIFO being head of line blocked due to the fact that it relies on the flow
      control high water mark to determine when it is acceptable for the Tx to
      place a packet in the Rx FIFO.
      
      The resolution for this is to set the FCRTH value to the RXPBSIZE - 32 so
      that even if the ring is almost completely full we can still place Tx
      packets on the Rx ring and drop incoming Rx traffic if we do not have
      sufficient space available in the Rx FIFO.
      Signed-off-by: NAlexander Duyck <alexander.h.duyck@intel.com>
      Tested-by: NSibai Li <sibai.li@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8f4a0a3d
  5. 17 3月, 2012 1 次提交
    • A
      ixgbe: Fix issues with SR-IOV loopback when flow control is disabled · c29f40ca
      Alexander Duyck 提交于
      This patch allows us to avoid a Tx hang when SR-IOV is enabled.  This hang
      can be triggered by sending small packets at a rate that was triggering Rx
      missed errors from the adapter while the internal Tx switch and at least
      one VF are enabled.
      
      This was all due to the fact that under heavy stress the Rx FIFO never
      drained below the flow control high water mark.  This resulted in the Tx
      FIFO being head of line blocked due to the fact that it relies on the flow
      control high water mark to determine when it is acceptable for the Tx to
      place a packet in the Rx FIFO.
      
      The resolution for this is to set the FCRTH value to the RXPBSIZE - 32 so
      that even if the ring is almost completely full we can still place Tx
      packets on the Rx ring and drop incoming Rx traffic if we do not have
      sufficient space available in the Rx FIFO.
      Signed-off-by: NAlexander Duyck <alexander.h.duyck@intel.com>
      Tested-by: NSibai Li <sibai.li@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      c29f40ca
  6. 14 3月, 2012 2 次提交
  7. 01 3月, 2012 1 次提交
  8. 03 2月, 2012 1 次提交
  9. 03 1月, 2012 1 次提交
  10. 20 12月, 2011 1 次提交
  11. 03 11月, 2011 1 次提交
  12. 17 10月, 2011 1 次提交
  13. 05 10月, 2011 1 次提交
  14. 29 9月, 2011 1 次提交
  15. 24 9月, 2011 1 次提交
  16. 29 8月, 2011 2 次提交
  17. 11 8月, 2011 1 次提交
  18. 04 8月, 2011 1 次提交
  19. 21 6月, 2011 2 次提交
  20. 06 6月, 2011 1 次提交
  21. 15 5月, 2011 1 次提交
  22. 05 5月, 2011 1 次提交
  23. 14 4月, 2011 5 次提交
  24. 08 3月, 2011 5 次提交
  25. 03 3月, 2011 3 次提交