On the at91sam9x5 SoC series, GPIO banks B and D only have 19 and 22
pins. So add a property to set this parameter.
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Fix also the reg size as we have 512 bytes bank not 256 bytes per gpio/mux
controller
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Tested-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add TWI nodes for atmel SoCs but keep i2c-gpio ones in order to let the
choice to the user in dts files.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

Add a third cell to define irq priority.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Reviewed-by: NRob Herring <rob.herring@calxeda.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

These were incorrectly introduced and can cause problems for of_irq_init.

The correct way to define a root controller is no interrupt-parent set at
all or the interrupt-parent is set to the root controller itself when
inherited from a parent node.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Tested-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Because of the inclusion of skeleton.dtsi, the memory node is
named "memory" we where not modifying the already included one
but creating a new one. It caused bad memory node detection during
early_init_dt_scan_memory() so we modify them.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: devicetree-discuss@lists.ozlabs.org

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

make the ECHI depends on ARCH_AT91
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: devicetree-discuss@lists.ozlabs.org

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: devicetree-discuss@lists.ozlabs.org

Use a string to specific the wakeup mode to make it more readable.

Add the Real-time Clock Wake-up support too for sam9g45 and sam9x5.
Add AT91_SHDW_CPTWK0_MAX to specific the Max of the Wakeup Counter.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

We can now drop the call to ioremap_registers() as we have the binding for the
SDRAM/DDR Controller.

Drop ioremap_registers() for sam9x5 too.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Specified the main Oscillator via clock binding.
This will allow to do not hardcode it anymore in the DT board at 12MHz.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

For now on use i2c-gpio driver on the same pin as the hardware IP.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>

Enable the nand in the cpu module with the partition.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

This patch adds the support for new PIO controller found on some
at91sam SOCs.
- more peripheral multiplexing
- more features to configure on a PIO (pull-down, Schmitt trigger, debouncer)
- support for several IRQ triggering features (type and polarity)

Support for those new features are retrieved from the device tree
compatibility string.

Debugfs at91_gpio file is updated to monitor configuration.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add "legacy" type of irqdomain to preserve old-style numbering
and allow smooth transition for both DT and non-DT cases.

Original idea and code by Jean-Christophe Plagniol-Villard.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Device tree include file for the AT91SAM9x5 SoC family.
An additional .dtsi file is created to describe the generic
SAM9x5 CPU Module (CM).
Device tree source files for each Evaluation Kit that are using
the generic CPU Module and the carrier board. The selection of
available peripherals is done in this .dts file.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>