1. 22 9月, 2012 1 次提交
  2. 11 9月, 2012 2 次提交
  3. 07 9月, 2012 21 次提交
  4. 06 9月, 2012 2 次提交
  5. 17 8月, 2012 1 次提交
  6. 19 4月, 2012 1 次提交
  7. 10 4月, 2012 1 次提交
    • S
      omap-serial: Fix the error handling in the omap_serial probe · 388bc262
      Shubhrajyoti D 提交于
      The patch does the following
      
      - The pm_runtime_disable is called in the remove not in the error
        case of probe.The patch calls the pm_runtime_disable in the error
        case.
      - Calls pm_runtime_put in the error case.
      - The  up is not freed in the error path. Fix the memory leak by using
        devm_* so that the memory need not be freed in the driver.
      - Also the iounmap is not called fix the same by calling using devm_ioremap.
      - Make the name of the error tags more meaningful.
      
      Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
      Cc: Govindraj.R <govindraj.raja@ti.com>
      Signed-off-by: NShubhrajyoti D <shubhrajyoti@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      388bc262
  8. 09 3月, 2012 1 次提交
  9. 10 2月, 2012 3 次提交
    • P
      tty: serial: omap-serial: wakeup latency constraint is in microseconds, not milliseconds · 19723452
      Paul Walmsley 提交于
      The receive FIFO wakeup latency estimate in the omap-serial driver is
      three orders of magnitude too small.  This effectively prevents the
      MPU from going to a low-power state when CONFIG_CPU_IDLE=y.  This is a
      major power management regression and masks some other FIFO-related
      bugs in the driver.
      
      Fix by correcting the most egregious problem in the RX wakeup latency
      estimate.  There are several other flaws in the estimator; these will
      be fixed by a separate patch series intended for 3.4.
      
      The difference in low-power states with this patch can be observed via
      debugfs in pm_debug/count.
      
      This estimate does not have any effect when CONFIG_CPU_IDLE=n.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Acked-by: NGovindraj.R <govindraj.raja@ti.com>
      Reviewed-by: NKevin Hilman <khilman@ti.com>
      Tested-by: NKevin Hilman <khilman@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      19723452
    • P
      tty: serial: OMAP: block idle while the UART is transferring data in PIO mode · be4b0281
      Paul Walmsley 提交于
      Prevent OMAP UARTs from going idle while they are still transferring
      data in PIO mode.  This works around an oversight in the OMAP UART
      hardware present in OMAP34xx and earlier: an idle UART won't send a
      wakeup when the TX FIFO threshold is reached.  This causes long delays
      during data transmission when the MPU powerdomain enters a low-power
      mode.  The MPU interrupt controller is not able to respond to
      interrupts when it's in a low-power state, so the TX buffer is not
      refilled until another wakeup event occurs.
      
      This fix changes the erratum i291 DMA idle workaround.  Rather than
      toggling between force-idle and no-idle, it will toggle between
      smart-idle and no-idle.  The important part of the workaround is the
      no-idle part, so this shouldn't result in any change in behavior.
      
      This fix should work on all OMAP UARTs.  Future patches intended for
      the 3.4 merge window will make this workaround conditional on a
      "feature" flag, and will use the OMAP36xx+ TX event wakeup support.
      
      Thanks to Kevin Hilman <khilman@ti.com> for mentioning the erratum i291
      workaround, which led to the development of this approach.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Acked-by: NGovindraj.R <govindraj.raja@ti.com>
      Reviewed-by: NKevin Hilman <khilman@ti.com>
      Tested-by: NKevin Hilman <khilman@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      be4b0281
    • P
      tty: serial: OMAP: use a 1-byte RX FIFO threshold in PIO mode · 0ba5f668
      Paul Walmsley 提交于
      In the (default) PIO mode, use a one-byte RX FIFO threshold.  The OMAP
      UART IP blocks do not appear to be capable of waking the system under
      an RX timeout condition.  Since the previous RX FIFO threshold was 16
      bytes, this meant that omap-serial.c did not become aware of any
      received data until all those bytes arrived or until another UART
      interrupt occurred.  This made the serial console and presumably other
      serial applications (GPS, serial Bluetooth) unusable or extremely
      slow.  A 1-byte RX FIFO threshold also allows the MPU to enter a
      low-power consumption state while waiting for the FIFO to fill.
      
      This can be verified using the serial console by comparing the
      behavior when "0123456789abcde" is pasted in from another window, with
      the behavior when "0123456789abcdef" is pasted in.  Since the former
      string is less than sixteen bytes long, the string is not echoed for
      some time, while the latter string is echoed immediately.
      
      DMA operation is unaffected by this patch.
      
      Thanks to Russell King - ARM Linux <linux@arm.linux.org.uk> for some
      additional information on the standard behavior of the RX timeout
      event, which was used to improve this commit description.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Govindraj Raja <govindraj.r@ti.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Reviewed-by: NKevin Hilman <khilman@ti.com>
      Tested-by: NKevin Hilman <khilman@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      0ba5f668
  10. 03 2月, 2012 3 次提交
    • P
      tty: serial: omap-serial: wakeup latency constraint is in microseconds, not milliseconds · 6bbcbf22
      Paul Walmsley 提交于
      The receive FIFO wakeup latency estimate in the omap-serial driver is
      three orders of magnitude too small.  This effectively prevents the
      MPU from going to a low-power state when CONFIG_CPU_IDLE=y.  This is a
      major power management regression and masks some other FIFO-related
      bugs in the driver.
      
      Fix by correcting the most egregious problem in the RX wakeup latency
      estimate.  There are several other flaws in the estimator; these will
      be fixed by a separate patch series intended for 3.4.
      
      The difference in low-power states with this patch can be observed via
      debugfs in pm_debug/count.
      
      This estimate does not have any effect when CONFIG_CPU_IDLE=n.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Acked-by: NGovindraj.R <govindraj.raja@ti.com>
      Reviewed-by: NKevin Hilman <khilman@ti.com>
      Tested-by: NKevin Hilman <khilman@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      6bbcbf22
    • P
      tty: serial: OMAP: block idle while the UART is transferring data in PIO mode · edbe5dbe
      Paul Walmsley 提交于
      Prevent OMAP UARTs from going idle while they are still transferring
      data in PIO mode.  This works around an oversight in the OMAP UART
      hardware present in OMAP34xx and earlier: an idle UART won't send a
      wakeup when the TX FIFO threshold is reached.  This causes long delays
      during data transmission when the MPU powerdomain enters a low-power
      mode.  The MPU interrupt controller is not able to respond to
      interrupts when it's in a low-power state, so the TX buffer is not
      refilled until another wakeup event occurs.
      
      This fix changes the erratum i291 DMA idle workaround.  Rather than
      toggling between force-idle and no-idle, it will toggle between
      smart-idle and no-idle.  The important part of the workaround is the
      no-idle part, so this shouldn't result in any change in behavior.
      
      This fix should work on all OMAP UARTs.  Future patches intended for
      the 3.4 merge window will make this workaround conditional on a
      "feature" flag, and will use the OMAP36xx+ TX event wakeup support.
      
      Thanks to Kevin Hilman <khilman@ti.com> for mentioning the erratum i291
      workaround, which led to the development of this approach.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Acked-by: NGovindraj.R <govindraj.raja@ti.com>
      Reviewed-by: NKevin Hilman <khilman@ti.com>
      Tested-by: NKevin Hilman <khilman@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      edbe5dbe
    • P
      tty: serial: OMAP: use a 1-byte RX FIFO threshold in PIO mode · 5816269e
      Paul Walmsley 提交于
      In the (default) PIO mode, use a one-byte RX FIFO threshold.  The OMAP
      UART IP blocks do not appear to be capable of waking the system under
      an RX timeout condition.  Since the previous RX FIFO threshold was 16
      bytes, this meant that omap-serial.c did not become aware of any
      received data until all those bytes arrived or until another UART
      interrupt occurred.  This made the serial console and presumably other
      serial applications (GPS, serial Bluetooth) unusable or extremely
      slow.  A 1-byte RX FIFO threshold also allows the MPU to enter a
      low-power consumption state while waiting for the FIFO to fill.
      
      This can be verified using the serial console by comparing the
      behavior when "0123456789abcde" is pasted in from another window, with
      the behavior when "0123456789abcdef" is pasted in.  Since the former
      string is less than sixteen bytes long, the string is not echoed for
      some time, while the latter string is echoed immediately.
      
      DMA operation is unaffected by this patch.
      
      Thanks to Russell King - ARM Linux <linux@arm.linux.org.uk> for some
      additional information on the standard behavior of the RX timeout
      event, which was used to improve this commit description.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Govindraj Raja <govindraj.r@ti.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Reviewed-by: NKevin Hilman <khilman@ti.com>
      Tested-by: NKevin Hilman <khilman@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      5816269e
  11. 27 1月, 2012 2 次提交
  12. 25 1月, 2012 2 次提交
    • P
      tty: serial: OMAP: transmit FIFO threshold interrupts don't wake the chip · 43cf7c0b
      Paul Walmsley 提交于
      It seems that when the transmit FIFO threshold is reached on OMAP
      UARTs, it does not result in a PRCM wakeup.  This appears to be a
      silicon bug.  This means that if the MPU powerdomain is in a low-power
      state, the MPU will not be awakened to refill the FIFO until the next
      interrupt from another device.
      
      The best solution, at least for the short term, would be for the OMAP
      serial driver to call a OMAP subarchitecture function to prevent the
      MPU powerdomain from entering a low power state while the FIFO has
      data to transmit.  However, we no longer have a clean way to do this,
      since patches that add platform_data function pointers have been
      deprecated by the OMAP maintainer.  So we attempt to work around this
      as well.  The workarounds depend on the setting of CONFIG_CPU_IDLE.
      
      When CONFIG_CPU_IDLE=n, the driver will now only transmit one byte at
      a time.  This causes the transmit FIFO threshold interrupt to stay
      active until there is no more data to be sent.  Thus, the MPU
      powerdomain stays on during transmits.  Aside from that energy
      consumption penalty, each transmitted byte results in a huge number of
      UART interrupts -- about five per byte.  This wastes CPU time and is
      quite inefficient, but is probably the most expedient workaround in
      this case.
      
      When CONFIG_CPU_IDLE=y, there is a slightly more direct workaround:
      the PM QoS constraint can be abused to keep the MPU powerdomain on.
      This results in a normal number of interrupts, but, similar to the
      above workaround, wastes power by preventing the MPU from entering
      WFI.
      
      Future patches are planned for the 3.4 merge window to implement more
      efficient, but also more disruptive, workarounds to these problems.
      
      DMA operation is unaffected by this patch.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Govindraj Raja <govindraj.r@ti.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      43cf7c0b
    • P
      tty: serial: OMAP: ensure FIFO levels are set correctly in non-DMA mode · 0a697b22
      Paul Walmsley 提交于
      Ensure FIFO levels are set correctly in non-DMA mode (the default).
      This patch will cause a receive FIFO threshold interrupt to be raised when
      there is at least one byte in the RX FIFO.  It will also cause a transmit
      FIFO threshold interrupt when there is only one byte remaining in the TX
      FIFO.
      
      These changes fix the receive interrupt problem and part of the
      transmit interrupt problem.  A separate set of issues must be worked
      around for the transmit path to have a basic level of functionality; a
      subsequent patch will address these.
      
      DMA operation is unaffected by this patch.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Govindraj Raja <govindraj.r@ti.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      0a697b22