1. 19 1月, 2015 8 次提交
    • N
      mmc: omap_hsmmc: remove prepare/complete system suspend support. · 61bd8a04
      NeilBrown 提交于
      The only function of these 'prepare' and 'complete' is to
      disable the 'card detect' irq during suspend.
      
      The commit which added this,
      commit a48ce884
          mmc: omap_hsmmc: Introduce omap_hsmmc_prepare/complete
      
      justified it by the need to avoid the registration of new devices
      during suspend.
      However mmc_pm_notify will set ->rescan_disable in the 'prepare'
      stage and clear it in the 'complete' stage, so no card detection
      will actually happen.
      Also the interrupt will be disabled before final suspend as part
      of common suspend processing.
      
      So this disabling of the interrupt is unnecessary, and interferes
      with a transition to using common code for card-detect management.
      
      Cc: Felipe Balbi <balbi@ti.com>
      Cc: Venkatraman S <svenkatr@ti.com>
      Cc: Chris Ball <cjb@laptop.org>
      Signed-off-by: NNeilBrown <neilb@suse.de>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      61bd8a04
    • A
      mmc: toshsd: Fix unbalanced locking · 8a66fdae
      Axel Lin 提交于
      Fix returning IRQ_HANDLED with spin_lock held.
      Signed-off-by: NAxel Lin <axel.lin@ingics.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      8a66fdae
    • W
      mmc: toshsd: use module_pci_driver to simplify the code · 1818681c
      Wei Yongjun 提交于
      Use the module_pci_driver() macro to make the code simpler
      by eliminating module_init and module_exit calls.
      Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      1818681c
    • A
      mmc: sdhci: Fix FSL ESDHC reset handling quirk · 304f0a98
      Alessio Igor Bogani 提交于
      The commit 0718e59a ("mmc: sdhci: move FSL ESDHC reset handling quirk into
      esdhc code") states that Freescale esdhc is the only controller which needs
      the interrupt registers restored after a reset. So it moves
      SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET quirk handling code into the
      esdhc-imx driver only. Unfortunately the same controller is used in
      other boards which use the of-esdhc driver instead (like powerpc P2020).
      
      Restore interrupts after reset in the sdhci-of-esdhc driver also.
      Signed-off-by: NAlessio Igor Bogani <alessio.bogani@elettra.eu>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      304f0a98
    • M
      mmc: sdhci-sirf: add sirf tuning function (cmd 19) · fc0b638a
      Minda Chen 提交于
      Add manual tuning function in CSR atlas7 SoC. It is mainly used
      for the UHS-I SD card working SDR50 SDR104 mode.
      
      The tuning principle can be seen in SD spec part1 v3.01 4.2.4.5
      (tuning command).
      
      SD host send the cmd19 and set the delay value(0-127).
      and the sdcard return 64 bytes data. If the data is same with
      the tuning data. The delay value is valid. Execute this commmand
      128 times. And calculate the longest window of the valid values.
      The value in the middle of this window is the best value.
      Signed-off-by: NMinda Chen <Minda.Chen@csr.com>
      Signed-off-by: NBarry Song <Baohua.Song@csr.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      fc0b638a
    • D
      mmc: dw_mmc: Protect read-modify-write of INTMASK with a lock · f8c58c11
      Doug Anderson 提交于
      We're running into cases where our enabling of the SDIO interrupt in
      dw_mmc doesn't actually take effect.  Specifically, adding patch like
      this:
      
       +++ b/drivers/mmc/host/dw_mmc.c
       @@ -1076,6 +1076,9 @@ static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
      
            mci_writel(host, INTMASK,
                 (int_mask | SDMMC_INT_SDIO(slot->id)));
       +    int_mask = mci_readl(host, INTMASK);
       +    if (!(int_mask & SDMMC_INT_SDIO(slot->id)))
       +      dev_err(&mmc->class_dev, "failed to enable sdio irq\n");
          } else {
      
      ...actually triggers the error message.  That's because the
      dw_mci_enable_sdio_irq() unsafely does a read-modify-write of the
      INTMASK register.
      
      We can't just use the standard host->lock since that lock is not irq
      safe and mmc_signal_sdio_irq() (called from interrupt context) calls
      dw_mci_enable_sdio_irq().  Add a new irq-safe lock to protect INTMASK.
      
      An alternate solution to this is to punt mmc_signal_sdio_irq() to the
      tasklet and then protect INTMASK modifications by the standard host
      lock.  This seemed like a bit more of a high-latency change.
      Reported-by: NBing Zhao <bzhao@marvell.com>
      Signed-off-by: NDoug Anderson <dianders@chromium.org>
      Reviewed-by: NJames Hogan <james.hogan@imgtec.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      f8c58c11
    • D
      mmc: dw_mmc: Cleanup disable of low power mode w/ SDIO interrupts · b24c8b26
      Doug Anderson 提交于
      In the patch (9623b5b9 mmc: dw_mmc: Disable low power mode if SDIO
      interrupts are used) I added code that disabled the low power mode of
      dw_mmc when SDIO interrupts are used.  That code worked but always
      felt a little hacky because we ended up disabling low power as a side
      effect of the first enable_sdio_irq() call.  That wouldn't be so bad
      except that disabling low power involves a complicated process of
      writing to the CMD/CMDARG registers and that extra process makes it
      difficult to cleanly the read-modify-write race in
      dw_mci_enable_sdio_irq() (see future patch in the series).
      
      Change the code to take advantage of the init_card() callback of the
      mmc core to do this right at bootup.
      Signed-off-by: NDoug Anderson <dianders@chromium.org>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      b24c8b26
    • D
      mmc: core: Support the optional init_card() callback for MMC and SD · eac86321
      Doug Anderson 提交于
      In (3fcb027d ARM: MXC: mxcmmc: work around a bug in the SDHC busy line
      handling) the optional init_card() callback was added.  According to
      the original change it was "for now only called from
      mmc_sdio_init_card()".
      
      This callback really ought to be called from the SD and MMC init
      functions as well.  One current user of this callback
      (mxcmci_init_card) will not work as expected if you insert an SDIO
      card, then eject it and put a normal SD card in.  Specifically the
      normal SD card will not get to run with 4-bit data.
      
      I'd like to use the init_card() callback to handle a similar quirk on
      dw_mmc when using SDIO Interrupts (the "low power" feature of the card
      needs to be disabled), so that will add a second user of the function.
      Signed-off-by: NDoug Anderson <dianders@chromium.org>
      Reviewed-by: NGrant Grundler <grundler@chromium.org>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      eac86321
  2. 18 1月, 2015 3 次提交
  3. 17 1月, 2015 2 次提交
  4. 15 1月, 2015 8 次提交
  5. 14 1月, 2015 9 次提交
    • T
      mmc: sdhci: Set SDHCI_POWER_ON with external vmmc · 3cbc6123
      Tim Kryger 提交于
      Host controllers lacking the required internal vmmc regulator may still
      follow the spec with regard to the LSB of SDHCI_POWER_CONTROL.  Set the
      SDHCI_POWER_ON bit when vmmc is enabled to encourage the controller to
      to drive CMD, DAT, SDCLK.
      
      This fixes a regression observed on some Qualcomm and Nvidia boards
      caused by 52221610 mmc: sdhci: Improve external VDD regulator support.
      
      Fixes: 52221610 (mmc: sdhci: Improve external VDD regulator support)
      Signed-off-by: NTim Kryger <tim.kryger@gmail.com>
      Tested-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      3cbc6123
    • S
      net: fec: fix MDIO bus assignement for dual fec SoC's · 3d125f9c
      Stefan Agner 提交于
      On i.MX28, the MDIO bus is shared between the two FEC instances.
      The driver makes sure that the second FEC uses the MDIO bus of the
      first FEC. This is done conditionally if FEC_QUIRK_ENET_MAC is set.
      However, in newer designs, such as Vybrid or i.MX6SX, each FEC MAC
      has its own MDIO bus. Simply removing the quirk FEC_QUIRK_ENET_MAC
      is not an option since other logic, triggered by this quirk, is
      still needed.
      
      Furthermore, there are board designs which use the same MDIO bus
      for both PHY's even though the second bus would be available on the
      SoC side. Such layout are popular since it saves pins on SoC side.
      Due to the above quirk, those boards currently do work fine. The
      boards in the mainline tree with such a layout are:
      - Freescale Vybrid Tower with TWR-SER2 (vf610-twr.dts)
      - Freescale i.MX6 SoloX SDB Board (imx6sx-sdb.dts)
      
      This patch adds a new quirk FEC_QUIRK_SINGLE_MDIO for i.MX28, which
      makes sure that the MDIO bus of the first FEC is used in any case.
      
      However, the boards above do have a SoC with a MDIO bus for each FEC
      instance. But the PHY's are not connected in a 1:1 configuration. A
      proper device tree description is needed to allow the driver to
      figure out where to find its PHY. This patch fixes that shortcoming
      by adding a MDIO bus child node to the first FEC instance, along
      with the two PHY's on that bus, and making use of the phy-handle
      property to add a reference to the PHY's.
      Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3d125f9c
    • D
      xen-netfront: use different locks for Rx and Tx stats · 900e1833
      David Vrabel 提交于
      In netfront the Rx and Tx path are independent and use different
      locks.  The Tx lock is held with hard irqs disabled, but Rx lock is
      held with only BH disabled.  Since both sides use the same stats lock,
      a deadlock may occur.
      
        [ INFO: possible irq lock inversion dependency detected ]
        3.16.2 #16 Not tainted
        ---------------------------------------------------------
        swapper/0/0 just changed the state of lock:
         (&(&queue->tx_lock)->rlock){-.....}, at: [<c03adec8>]
        xennet_tx_interrupt+0x14/0x34
        but this lock took another, HARDIRQ-unsafe lock in the past:
         (&stat->syncp.seq#2){+.-...}
        and interrupts could create inverse lock ordering between them.
        other info that might help us debug this:
         Possible interrupt unsafe locking scenario:
      
               CPU0                    CPU1
               ----                    ----
          lock(&stat->syncp.seq#2);
                                       local_irq_disable();
                                       lock(&(&queue->tx_lock)->rlock);
                                       lock(&stat->syncp.seq#2);
          <Interrupt>
            lock(&(&queue->tx_lock)->rlock);
      
      Using separate locks for the Rx and Tx stats fixes this deadlock.
      Reported-by: NDmitry Piotrovsky <piotrovskydmitry@gmail.com>
      Signed-off-by: NDavid Vrabel <david.vrabel@citrix.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      900e1833
    • M
      drivers: net: cpsw: fix multicast flush in dual emac mode · 25906052
      Mugunthan V N 提交于
      Since ALE table is a common resource for both the interfaces in Dual EMAC
      mode and while bringing up the second interface in cpsw_ndo_set_rx_mode()
      all the multicast entries added by the first interface is flushed out and
      only second interface multicast addresses are added. Fixing this by
      flushing multicast addresses based on dual EMAC port vlans which will not
      affect the other emac port multicast addresses.
      
      Fixes: d9ba8f9e (driver: net: ethernet: cpsw: dual emac interface implementation)
      Cc: <stable@vger.kernel.org> # v3.9+
      Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      25906052
    • S
      leds: netxbig: fix oops at probe time · 0c86ac2c
      Simon Guinot 提交于
      This patch fixes a NULL pointer dereference on led_dat->mode_val. Due to
      this bug, a kernel oops can be observed at probe time on the LaCie 2Big
      and 5Big v2 boards:
      
      Unable to handle kernel NULL pointer dereference at virtual address 00000008
      [...]
      [<c03f244c>] (netxbig_led_probe) from [<c02c8c6c>] (platform_drv_probe+0x4c/0x9c)
      [<c02c8c6c>] (platform_drv_probe) from [<c02c72d0>] (driver_probe_device+0x98/0x25c)
      [<c02c72d0>] (driver_probe_device) from [<c02c7520>] (__driver_attach+0x8c/0x90)
      [<c02c7520>] (__driver_attach) from [<c02c5c24>] (bus_for_each_dev+0x68/0x94)
      [<c02c5c24>] (bus_for_each_dev) from [<c02c6408>] (bus_add_driver+0x124/0x1dc)
      [<c02c6408>] (bus_add_driver) from [<c02c7ac0>] (driver_register+0x78/0xf8)
      [<c02c7ac0>] (driver_register) from [<c000888c>] (do_one_initcall+0x80/0x1cc)
      [<c000888c>] (do_one_initcall) from [<c0733618>] (kernel_init_freeable+0xe4/0x1b4)
      [<c0733618>] (kernel_init_freeable) from [<c058db9c>] (kernel_init+0xc/0xec)
      [<c058db9c>] (kernel_init) from [<c0009850>] (ret_from_fork+0x14/0x24)
      [...]
      
      This bug was introduced by commit 588a6a99
      ("leds: netxbig: fix attribute-creation race").
      Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org>
      Cc: <stable@vger.kernel.org> # 3.17+
      Acked-by: NJohan Hovold <johan@kernel.org>
      Signed-off-by: NBryan Wu <cooloney@gmail.com>
      0c86ac2c
    • H
      cxgb4vf: Initialize mdio_addr before using it · fd48e639
      Hariprasad Shenai 提交于
      In commit 5ad24def ("cxgb4vf: Fix ethtool get_settings for VF driver")
      mdio_addr of port_info structure was used unininitialzed. Fixing it.
      Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fd48e639
    • J
      clk: berlin: bg2q: remove non-exist "smemc" gate clock · b71e8ecd
      Jisheng Zhang 提交于
      The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable
      register is for nfc. Current code use bit19 for non-exist "smemc"
      incorrectly, this prevents eMMC from working due to the sdhci's
      "core" clk is still gated.
      Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
      Cc: stable@vger.kernel.org # 3.16+
      Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      b71e8ecd
    • B
      clk: at91: keep slow clk enabled to prevent system hang · dca1a4b5
      Boris Brezillon 提交于
      All slow clk users are not properly claiming it (get + prepare + enable)
      before using it.
      If all users properly claiming this clock release it, the clock is
      disabled, but faulty users still depends on it, and the system hangs.
      
      This fix prevents the slow clock from being disabled, and should solve the
      hanging issue, but offending drivers should be patched to properly claim
      this clock.
      Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
      Reported-by: NBo Shen <voice.shen@atmel.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      dca1a4b5
    • A
      dmaengine: dw: balance PM runtime calls · 6acf3998
      Andy Shevchenko 提交于
      In case of PCI driver we will get a warning:
      	dw_dmac_pci 0000:00:18.0: Unbalanced pm_runtime_enable!
      	dw_dmac_pci 0000:00:18.0: DesignWare DMA Controller, 8 channels
      
      This happens due to pm_runtime_enable() call from the driver when PM runtime is
      enabled by core.
      
      This patch moves that call to the platform driver where it might make sense.
      
      Fixes: bb32baf7 (dmaengine: dw: enable runtime PM)
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      6acf3998
  6. 13 1月, 2015 10 次提交