ARMv7 hardware (S5Pv210 and Exynos SoCs) provides only 32 external
interrupts which can wakeup device from deep sleep modes.  On S5Pv210
these are gph0-gph3.  On all ARMv7 Exynos designs these are gpx0-gpx3.
There is only one 32-bit register for controlling the external wakeup
interrupt mask (masking and unmasking waking capability of these
interrupts).

This lead to implementation in pinctrl driver and machine code which was
using static memory for storing the mask value and not caring about
multiple devices of pin controller... because only one pin controller
device will be handling this.

Since each pin controller node in Device Tree maps onto one device, this
corresponds to hidden assumption in parsing the Device Tree: external
wakeup interrupts can be defined only once.  Make this assumption an
explicit requirement.

ARMv8 Exynos5433 and Exynos7 bring additional 32 external wakeup
interrupts (up to 64 total, banks gpa0-gpa3 and gpf1-gpf5) and another
32-bit wide register for controlling them.  Existing code does not
support it but anyway these additional interrupts will be belonging to
the same pin controller device/node.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>

Add missing compatible id for Exynos3250 SoC to device tree docs.
Exynos pin control driver supports it since commit d97f5b98
("pinctrl: exynos: Add driver data for Exynos3250").
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need
to support the multiple memory map because the registers of GPFx are located
in the different domain.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Update examples in Samsung pinctrl dt-bindings with new macros coming
from header file.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>

Add Samsung EXYNOS5410 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5410.
Signed-off-by: NHakjoo Kim <ruppi.kim@hardkernel.com>
[AF: Rebased onto Exynos5260, irq_chip consolidation, const'ification]
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Tested-by: NPavel Fedin <p.fedin@samsung.com>
[k.kozlowski: Rebased on current v4.3]
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

Audio IPs on Exynos7 require gpios available in AUDIO
pin controller block. So adding the AUDIO pinctrl support.
Signed-off-by: NPadmavathi Venna <padma.v@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.
Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Adding list of aliases for supported Exynos7 pin controller blocks.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds initial driver data for Exynos7 pinctrl support.
Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Tested-by: NThomas Abraham <thomas.ab@samsung.com>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Tested-by: NThomas Abraham <thomas.ab@samsung.com>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

This patch extends the range of settings configurable via pinfunc API
to cover pin value as well. This allows configuration of default values
of pins, which is useful for pins that are not supposed to be used by
any dedicated driver, but need certain board-specific setting.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

One of remaining limitations of current pinctrl-samsung driver was
the inability to parse multiple pinmux/pinconf group nodes grouped
inside a single device tree node. It made defining groups of pins for
single purpose, but with different parameters very inconvenient.

This patch implements Tegra-like support for grouping multiple pinctrl
groups inside one device tree node, by completely changing the way
pin groups and functions are parsed from device tree. The code creating
pinctrl maps from DT nodes has been borrowed from pinctrl-tegra, while
the initial creation of groups and functions has been completely
rewritten with following assumptions:
 - each group consists of just one pin and does not depend on data
   from device tree,
 - each function is represented by a device tree child node of the
   pin controller, which in turn can contain multiple child nodes
   for pins that need to have different configuration values.

Device Tree bindings are fully backwards compatible. New functionality
can be used by defining a new pinctrl group consisting of several child
nodes, as on following example:

	sd4_bus8: sd4-bus-width8 {
		part-1 {
			samsung,pins = "gpk0-3", "gpk0-4",
					"gpk0-5", "gpk0-6";
			samsung,pin-function = <3>;
			samsung,pin-pud = <3>;
			samsung,pin-drv = <3>;
		};
		part-2 {
			samsung,pins = "gpk1-3", "gpk1-4",
					"gpk1-5", "gpk1-6";
			samsung,pin-function = <4>;
			samsung,pin-pud = <4>;
			samsung,pin-drv = <3>;
		};
	};

Tested on Exynos4210-Trats board and a custom Exynos4212-based one.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Adds pinctrl support for all platforms based on EXYNOS5260 SoC.
Acked-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: NYoung-Gun Jang <yg1004.jang@samsung.com>
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch implements pinctrl support and adds device tree bindings
for s5pv210.
Signed-off-by: NMateusz Krawczuk <m.krawczuk@partner.samsung.com>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add Samsung EXYNOS5420 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5420.
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Tested-by : Sunil Joshi <joshi@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds examples to samsung-pinctrl.txt documentaion file
on how to make gpio binding and gpio request
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The s3c24xx pins follow a similar pattern as the other Samsung SoCs and
can therefore reuse the already introduced infrastructure.

The s3c24xx SoCs have one design oddity in that the first 4 external
interrupts do not reside in the eint pending register but in the main
interrupt controller instead. We solve this by forwarding the external
interrupt from the main controller into the irq domain of the pin bank.
The masking/acking of these interrupts is handled in the same way.

Furthermore the S3C2412/2413 SoCs contain another oddity in that they
keep the same 4 eints in the main interrupt controller and eintpend
register and requiring ack operations to happen in both. This is solved
by using different compatible properties for the wakeup eint node which
set a property accordingly.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds pinctrl-s3c64xx driver which implements pin control
interface for Samsung S3C64xx SoCs.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fix the incorrect compatible property value of pinctrl for EXYNOS4 SoCs.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch extends the driver with any necessary SoC-specific
definitions to support EXYNOS4X12 SoCs.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a new device tree enabled pinctrl and gpiolib driver for Samsung
SoC's. This driver provides a common and extensible framework for all
Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
driver supports only device tree based instantiation and hence can be
used only on those Samsung platforms that have device tree enabled.

This driver is split into two parts: the pinctrl interface and the gpiolib
interface. The pinctrl interface registers pinctrl devices with the pinctrl
subsystem and gpiolib interface registers gpio chips with the gpiolib
subsystem. The information about the pins, pin groups, pin functions and
gpio chips, which are SoC specific, are parsed from device tree node.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>