1. 02 10月, 2010 2 次提交
  2. 05 9月, 2010 1 次提交
  3. 26 8月, 2010 1 次提交
    • B
      x86, tsc: Remove CPU frequency calibration on AMD · acf01734
      Borislav Petkov 提交于
      6b37f5a2 introduced the CPU frequency
      calibration code for AMD CPUs whose TSCs didn't increment with the
      core's P0 frequency. From F10h, revB onward, however, the TSC increment
      rate is denoted by MSRC001_0015[24] and when this bit is set (which
      should be done by the BIOS) the TSC increments with the P0 frequency
      so the calibration is not needed and booting can be a couple of mcecs
      faster on those machines.
      
      Besides, there should be virtually no machines out there which don't
      have this bit set, therefore this calibration can be safely removed. It
      is a shaky hack anyway since it assumes implicitly that the core is in
      P0 when BIOS hands off to the OS, which might not always be the case.
      Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <20100825162823.GE26438@aftab>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      acf01734
  4. 19 8月, 2010 1 次提交
  5. 29 7月, 2010 4 次提交
  6. 10 6月, 2010 1 次提交
  7. 17 12月, 2009 1 次提交
  8. 12 12月, 2009 1 次提交
    • M
      x86: Limit the number of processor bootup messages · 2eaad1fd
      Mike Travis 提交于
      When there are a large number of processors in a system, there
      is an excessive amount of messages sent to the system console.
      It's estimated that with 4096 processors in a system, and the
      console baudrate set to 56K, the startup messages will take
      about 84 minutes to clear the serial port.
      
      This set of patches limits the number of repetitious messages
      which contain no additional information.  Much of this information
      is obtainable from the /proc and /sysfs.   Some of the messages
      are also sent to the kernel log buffer as KERN_DEBUG messages so
      dmesg can be used to examine more closely any details specific to
      a problem.
      
      The new cpu bootup sequence for system_state == SYSTEM_BOOTING:
      
      Booting Node   0, Processors  #1 #2 #3 #4 #5 #6 #7 Ok.
      Booting Node   1, Processors  #8 #9 #10 #11 #12 #13 #14 #15 Ok.
      ...
      Booting Node   3, Processors  #56 #57 #58 #59 #60 #61 #62 #63 Ok.
      Brought up 64 CPUs
      
      After the system is running, a single line boot message is displayed
      when CPU's are hotplugged on:
      
          Booting Node %d Processor %d APIC 0x%x
      
      Status of the following lines:
      
          CPU: Physical Processor ID:		printed once (for boot cpu)
          CPU: Processor Core ID:		printed once (for boot cpu)
          CPU: Hyper-Threading is disabled	printed once (for boot cpu)
          CPU: Thermal monitoring enabled	printed once (for boot cpu)
          CPU %d/0x%x -> Node %d:		removed
          CPU %d is now offline:		only if system_state == RUNNING
          Initializing CPU#%d:		KERN_DEBUG
      Signed-off-by: NMike Travis <travis@sgi.com>
      LKML-Reference: <4B219E28.8080601@sgi.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      2eaad1fd
  9. 24 11月, 2009 1 次提交
  10. 21 9月, 2009 1 次提交
  11. 16 9月, 2009 1 次提交
  12. 04 9月, 2009 2 次提交
  13. 01 9月, 2009 1 次提交
  14. 11 8月, 2009 1 次提交
  15. 23 7月, 2009 1 次提交
  16. 11 7月, 2009 1 次提交
  17. 21 6月, 2009 1 次提交
    • A
      x86: Set cpu_llc_id on AMD CPUs · 99bd0c0f
      Andreas Herrmann 提交于
      This counts when building sched domains in case NUMA information
      is not available.
      
      ( See cpu_coregroup_mask() which uses llc_shared_map which in turn is
        created based on cpu_llc_id. )
      
      Currently Linux builds domains as follows:
      (example from a dual socket quad-core system)
      
       CPU0 attaching sched-domain:
        domain 0: span 0-7 level CPU
         groups: 0 1 2 3 4 5 6 7
      
        ...
      
       CPU7 attaching sched-domain:
        domain 0: span 0-7 level CPU
         groups: 7 0 1 2 3 4 5 6
      
      Ever since that is borked for multi-core AMD CPU systems.
      This patch fixes that and now we get a proper:
      
       CPU0 attaching sched-domain:
        domain 0: span 0-3 level MC
         groups: 0 1 2 3
         domain 1: span 0-7 level CPU
          groups: 0-3 4-7
      
        ...
      
       CPU7 attaching sched-domain:
        domain 0: span 4-7 level MC
         groups: 7 4 5 6
         domain 1: span 0-7 level CPU
          groups: 4-7 0-3
      
      This allows scheduler to assign tasks to cores on different sockets
      (i.e. that don't share last level cache) for performance reasons.
      Signed-off-by: NAndreas Herrmann <andreas.herrmann3@amd.com>
      LKML-Reference: <20090619085909.GJ5218@alberich.amd.com>
      Cc: <stable@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      99bd0c0f
  18. 09 6月, 2009 1 次提交
    • A
      x86: Detect use of extended APIC ID for AMD CPUs · 42937e81
      Andreas Herrmann 提交于
      Booting a 32-bit kernel on Magny-Cours results in the following panic:
      
        ...
        Using APIC driver default
        ...
        Overriding APIC driver with bigsmp
        ...
        Getting VERSION: 80050010
        Getting VERSION: 80050010
        Getting ID: 10000000
        Getting ID: ef000000
        Getting LVT0: 700
        Getting LVT1: 10000
        Kernel panic - not syncing: Boot APIC ID in local APIC unexpected (16 vs 0)
        Pid: 1, comm: swapper Not tainted 2.6.30-rcX #2
        Call Trace:
         [<c05194da>] ? panic+0x38/0xd3
         [<c0743102>] ? native_smp_prepare_cpus+0x259/0x31f
         [<c073b19d>] ? kernel_init+0x3e/0x141
         [<c073b15f>] ? kernel_init+0x0/0x141
         [<c020325f>] ? kernel_thread_helper+0x7/0x10
      
      The reason is that default_get_apic_id handled extension of local APIC
      ID field just in case of XAPIC.
      
      Thus for this AMD CPU, default_get_apic_id() returns 0 and
      bigsmp_get_apic_id() returns 16 which leads to the respective kernel
      panic.
      
      This patch introduces a Linux specific feature flag to indicate
      support for extended APIC id (8 bits instead of 4 bits width) and sets
      the flag on AMD CPUs if applicable.
      Signed-off-by: NAndreas Herrmann <andreas.herrmann3@amd.com>
      Cc: <stable@kernel.org>
      LKML-Reference: <20090608135509.GA12431@alberich.amd.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      42937e81
  19. 18 5月, 2009 1 次提交
  20. 29 4月, 2009 1 次提交
  21. 12 3月, 2009 1 次提交
  22. 08 3月, 2009 1 次提交
  23. 28 2月, 2009 1 次提交
    • J
      x86: AMD Support for perf_counter · f87ad35d
      Jaswinder Singh Rajput 提交于
      Supported basic performance counter for AMD K7 and later:
      
      $ perfstat -e 0,1,2,3,4,5,-1,-2,-3,-4,-5 ls > /dev/null
      
       Performance counter stats for 'ls':
      
            12.298610  task clock ticks     (msecs)
      
              3298477  CPU cycles           (events)
              1406354  instructions         (events)
               749035  cache references     (events)
                16939  cache misses         (events)
               100589  branches             (events)
                11159  branch misses        (events)
             7.627540  cpu clock ticks      (msecs)
            12.298610  task clock ticks     (msecs)
                  500  pagefaults           (events)
                    6  context switches     (events)
                    3  CPU migrations       (events)
      
       Wall-clock time elapsed:     8.672290 msecs
      Signed-off-by: NJaswinder Singh Rajput <jaswinderrajput@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f87ad35d
  24. 18 2月, 2009 2 次提交
  25. 29 1月, 2009 1 次提交
  26. 17 12月, 2008 1 次提交
    • V
      x86: support always running TSC on Intel CPUs · 40fb1715
      Venki Pallipadi 提交于
      Impact: reward non-stop TSCs with good TSC-based clocksources, etc.
      
      Add support for CPUID_0x80000007_Bit8 on Intel CPUs as well. This bit means
      that the TSC is invariant with C/P/T states and always runs at constant
      frequency.
      
      With Intel CPUs, we have 3 classes
      * CPUs where TSC runs at constant rate and does not stop n C-states
      * CPUs where TSC runs at constant rate, but will stop in deep C-states
      * CPUs where TSC rate will vary based on P/T-states and TSC will stop in deep
        C-states.
      
      To cover these 3, one feature bit (CONSTANT_TSC) is not enough. So, add a
      second bit (NONSTOP_TSC). CONSTANT_TSC indicates that the TSC runs at
      constant frequency irrespective of P/T-states, and NONSTOP_TSC indicates
      that TSC does not stop in deep C-states.
      
      CPUID_0x8000000_Bit8 indicates both these feature bit can be set.
      We still have CONSTANT_TSC _set_ and NONSTOP_TSC _not_set_ on some older Intel
      CPUs, based on model checks. We can use TSC on such CPUs for time, as long as
      those CPUs do not support/enter deep C-states.
      Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      40fb1715
  27. 16 10月, 2008 1 次提交
  28. 08 9月, 2008 3 次提交
  29. 06 9月, 2008 3 次提交
  30. 05 9月, 2008 1 次提交