提交 · 5f4e0be3a72325fbc4d349a847cc9b2edd85b6d2 · openanolis / cloud-kernel

29 12月, 2013 4 次提交

clk: sunxi: make factors_clk_setup return the clock it registers · 5f4e0be3

由 Emilio López 提交于 12月 23, 2013

We will be needing this to register a factor clock as parent with leaf
divisors on a single call.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMike Turquette <mturquette@linaro.org>

5f4e0be3

clk: sunxi: add gating support to PLL1 · d838ff33

由 Emilio López 提交于 12月 23, 2013

This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>

d838ff33

clk: sunxi: clean the magic number of mux parents · edaf3fb5

由 Emilio López 提交于 12月 23, 2013

This was pointed out during the review of the factor patches. Let's
indicate what does that magic 5 mean.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMike Turquette <mturquette@linaro.org>

edaf3fb5

clk: sunxi: register factors clocks behind composite · 40a5dcba

由 Emilio López 提交于 12月 23, 2013

This commit reworks factors clock registration to be done behind a
composite clock. This allows us to additionally add a gate, mux or
divisors, as it will be needed by some future PLLs.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>

40a5dcba

23 12月, 2013 4 次提交

clk: add accuracy support for fixed clock · 0903ea60

由 Boris BREZILLON 提交于 12月 21, 2013

This patch adds support for accuracy retrieval on fixed clocks.
It also adds a new dt property called 'clock-accuracy' to define the clock
accuracy.

This can be usefull for oscillator (RC, crystal, ...) definitions which are
always given an accuracy characteristic.
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

0903ea60

clk: add clk accuracy retrieval support · 5279fc40

由 Boris BREZILLON 提交于 12月 21, 2013

The clock accuracy is expressed in ppb (parts per billion) and represents
the possible clock drift.
Say you have a clock (e.g. an oscillator) which provides a fixed clock of
20MHz with an accuracy of +- 20Hz. This accuracy expressed in ppb is
20Hz/20MHz = 1000 ppb (or 1 ppm).

Clock users may need the clock accuracy information in order to choose
the best clock (the one with the best accuracy) across several available
clocks.

This patch adds clk accuracy retrieval support for common clk framework by
means of a new function called clk_get_accuracy.
This function returns the given clock accuracy expressed in ppb.

In order to get the clock accuracy, this implementation adds one callback
called recalc_accuracy to the clk_ops structure.
This callback is given the parent clock accuracy (if the clock is not a
root clock) and should recalculate the given clock accuracy.

This callback is optional and may be implemented if the clock is not
a perfect clock (accuracy != 0 ppb).
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

5279fc40

clk: si570: Remove redundant of_match_ptr helper · e8ab2f11

由 Sachin Kamat 提交于 12月 21, 2013

'clk_si570_of_match' is always compiled in. Hence the
helper macro is not needed.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

e8ab2f11

Merge tag 'renesas-clock-for-v3.14' of... · 6e1ee9b1

由 Mike Turquette 提交于 12月 22, 2013

Merge tag 'renesas-clock-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into clk-next-shmobile2

Renesas ARM based SoC Clock updates for v3.14

Add support for using emev2 SMU clocks with DT

6e1ee9b1

21 12月, 2013 2 次提交
- M
  Merge tag 'mvebu-clk-3.14' of git://git.infradead.org/linux-mvebu into clk-next · a5d37d22
  由 Mike Turquette 提交于 12月 20, 2013
```
mvebu clock changes for v3.14

 - mvebu: add the core divider clock driver
 - sparse cleanup
```
  a5d37d22
- M
  Merge tag 'zynq-clk-for-3.14-v2' of git://git.xilinx.com/linux-xlnx into clk-next · 7cba64cd
  由 Mike Turquette 提交于 12月 20, 2013
```
arm: Xilinx Zynq clk patches for v3.14

- Add support for fclk-enable feature
```
  7cba64cd
20 12月, 2013 9 次提交

clk/zynq/clkc: Add 'fclk-enable' feature · ba52f8a9

由 Soren Brinkmann 提交于 11月 27, 2013

In some use cases Zynq's FPGA clocks are used as static clock
generators for IP in the FPGA part of the SOC for which no Linux driver
exists and would control those clocks. To avoid automatic
gating of these clocks in such cases a new property - fclk-enable - is
added to the clock controller's DT description to accomodate such use
cases. It's value is a bitmask, where a set bit results in enabling
the corresponding FCLK through the clkc.

FPGA clocks are handled following the rules below:

If an FCLK is not enabled by bootloaders, that FCLK will be disabled in
Linux. Drivers can enable and control it through the CCF as usual.

If an FCLK is enabled by bootloaders AND the corresponding bit in the
'fclk-enable' DT property is set, that FCLK will be enabled by the clkc,
resulting in an off by one reference count for that clock. Ensuring it
will always be running.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

ba52f8a9

clk: ux500: Remove extra semicolon · 24c039f6