Almost all edac	drivers	initialize csrow_info->first_page,
csrow_info->last_page and csrow_info->page_mask. Those vars are
used inside the EDAC core, in order to calculate the csrow affected
by an error, by using the routine edac_mc_find_csrow_by_page().

However, very few drivers actually use it:
        e752x_edac.c
        e7xxx_edac.c
        i3000_edac.c
        i82443bxgx_edac.c
        i82860_edac.c
        i82875p_edac.c
        i82975x_edac.c
        r82600_edac.c

There also a few other drivers that have their own calculus
formula internally using those vars.

All the others are just wasting time by initializing those
data.

While initializing data without using them won't cause any troubles, as
those information is stored at the wrong place (at csrows structure), it
is better to remove what is unused, in order to simplify the next patch.
Reviewed-by: NAristeu Rozanski <arozansk@redhat.com>
Acked-by: NBorislav Petkov <borislav.petkov@amd.com>
Acked-by: NChris Metcalf <cmetcalf@tilera.com>
Cc: Doug Thompson <norsk5@yahoo.com>
Cc: Hitoshi Mitake <h.mitake@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com>
Cc: Josh Boyer <jwboyer@gmail.com>
Cc: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>

On systems based on chip select rows, all channels need to use memories
with the same properties, otherwise the memories on channels A and B
won't be recognized.

However, such assumption is not true for all types of memory
controllers.

Controllers for FB-DIMM's don't have such requirements.

Also, modern Intel controllers seem to be capable of handling such
differences.

So, we need to get rid of storing the DIMM information into a per-csrow
data, storing it, instead at the right place.

The first step is to move grain, mtype, dtype and edac_mode to the
per-dimm struct.
Reviewed-by: NAristeu Rozanski <arozansk@redhat.com>
Reviewed-by: NBorislav Petkov <borislav.petkov@amd.com>
Acked-by: NChris Metcalf <cmetcalf@tilera.com>
Cc: Doug Thompson <norsk5@yahoo.com>
Cc: Borislav Petkov <borislav.petkov@amd.com>
Cc: Mark Gross <mark.gross@intel.com>
Cc: Jason Uhlenkott <juhlenko@akamai.com>
Cc: Tim Small <tim@buttersideup.com>
Cc: Ranganathan Desikan <ravi@jetztechnologies.com>
Cc: "Arvind R." <arvino55@gmail.com>
Cc: Olof Johansson <olof@lixom.net>
Cc: Egor Martovetsky <egor@pasemi.com>
Cc: Michal Marek <mmarek@suse.cz>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Joe Perches <joe@perches.com>
Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Hitoshi Mitake <h.mitake@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: James Bottomley <James.Bottomley@parallels.com>
Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Josh Boyer <jwboyer@gmail.com>
Cc: Mike Williams <mike@mikebwilliams.com>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>

These const tables are currently marked __devinitdata, but
Documentation/PCI/pci.txt says:

"o The ID table array should be marked __devinitconst; this is done
automatically if the table is declared with DEFINE_PCI_DEVICE_TABLE()."

So use DEFINE_PCI_DEVICE_TABLE(x).

Based on PaX and earlier work by Andi Kleen.
Signed-off-by: NLionel Debroux <lionel_debroux@yahoo.fr>
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Fix DRAM chip select sizes calculation for K8, revisions D and E.

Reported-by: Niklas Söderlund <niklas.soderlund@ericsson.com
Link: http://lkml.kernel.org/r/1320849178-23340-1-git-send-email-niklas.soderlund@ericsson.comSigned-off-by: NBorislav Petkov <borislav.petkov@amd.com>

While initializing the array of csrow attribute instances, a few csrows
were uninitialized. This happened because the module only performed a
check for DRAM base ctl register0's and not DRAM base ctl register1's
chip select enable bit. There could be systems with DIMMs populated
on only single memory channel whereas the module also assumed that a
dual channel dimm had double the memory size of a single memory channel
instead of checking the memory on each channel.

This patch fixes these above issues.
Signed-off-by: NAshish Shenoy <ashenoy@riverbed.com>
Signed-off-by: NPrasanna S. Panchamukhi <ppanchamukhi@riverbed.com>
Link: http://lkml.kernel.org/r/4F459CFA.5090604@riverbed.comSigned-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Sparse complains that edac_cap was declared as dev_type and we are
returning edac_type.  Historically, edac_type was correct but since
then we have changed it to return a bit field.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Link: http://lkml.kernel.org/r/20111006063025.GA2615@mwandaSigned-off-by: NBorislav Petkov <borislav.petkov@amd.com>

When accessing the scrub rate control register (F3x58) on F15h, the DRAM
controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the
scrub rate configuration can take effect. See Erratum 505 in the AMD
F15h revision guide for more details.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Drop third nbcfg argument which is old remains and not required anymore.

No functionality change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h CPUs may report a non-DRAM address when reporting an error address
belonging to a CC6 state save area. Add a workaround to detect this
condition and compute the actual DRAM address of the error as documented
in the Revision Guide for AMD Family 15h Models 00h-0Fh Processors.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h and later use a portion of DRAM as a CC6 storage area. BIOS
programs D18F1x[17C:140,7C:40] DRAM Base/Limit accordingly by
subtracting the storage area from the DRAM limit setting. However, in
order for edac to consider that part of DRAM too, we need to include it
into the per-node range.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

This warning was wrongfully added for a normal condition - intlvsel
actually selects the destination node when node interleaving is enabled
and it is not a mismatch. For a detailed example, see section 2.8.10.2
"Node Interleaving" in F10h BKDG.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

This patch removes superfluous debugging output in the sysfs scrub rate
handler. It also consolidates the error handling in the scrub rate
accessors.
Signed-off-by: NMarkus Trippelsdorf <markus@trippelsdorf.de>
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

We check the pointers together but at least one of them could be invalid
due to failed allocation. Since we cannot continue if either of the two
allocations has failed, exit early by freeing them both.

Cc: <stable@kernel.org> # 38.x
Reported-by: NMauro Carvalho Chehab <mchehab@redhat.com>
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Those should all be unsigned.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Fix amd64_debug_display_dimm_sizes() arguments order per convention (pvt
is always first). Also, the now second arg denotes the DCT so adjust its
type.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

The dram ranges make sense only as an unsigned type.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Use the macro directly instead
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Adjust argument types to the PCI config API's types.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Return unsigned u8 values only.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

A node id can never be negative since we use it as an index into
the DRAM ranges array. This also makes one of the BUG_ON conditions
redundant.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add the PCI device ids required for driver registration. Remove
pvt->ctl_name and use the family descriptor directly, instead. Then,
bump driver version and fixup its format. Finally, enable DRAM ECC
decoding on F15h.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h has the same ECC symbol size options as F10h revD and later so
adjust checks to that. Simplify code a bit.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Drop per-instance variable and compute min scrubrate dynamically.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Drop static tables which map the bits in F2x80 to a chip select size in
favor of functions doing the mapping with some bit fiddling. Also, add
F15 support.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

This function is relevant for F10h and higher, and it has only one
callsite so drop its function pointer from the low_ops struct.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h sys_addr to chip select mapping is almost identical to F10h's so
reuse that. Rename functions on that path accordingly.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add paranoid checks for the sys address before going off and decoding
it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Replace per-DCT macros with smarter ones, drop hack and look for the
spare rank on all chip selects on a channel.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove the channel interleave select bit properly. See
F2x110[DctSelIntLvAddr] for details.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

When node interleaving is enabled, a subset of the addr[14:12] bits has
to be removed in order to get the normalized DCT address of the DRAM
channel. The actual number of bits to remove is determined by F1x[1,
0][7C:40][IntlvEn]. Do this correctly.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

On revC3 and revE Fam10h machines and later, non-interleaved graphics
framebuffer memory under the 16G mark can be swapped with a region
located at the bottom of memory so that the GPU can use the interleaved
region and thus two channels. Add support for that.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

The address bits from MC4_STATUS differ only between K8 and the rest so
no need for a per-family method.

No functional change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Use the struct mce directly instead of copying from it into a custom
struct err_regs.

No functionality change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

The only difference is that F10h used to sport ganged DCTs and F15h
doesn't so adjust the F10h routine and reuse it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove unused defines, drop family names from define names.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove reporting of errors with UC bit set - this is done by the MCE
decoding code anyway and this driver deals with DRAM ECC errors only. UC
(NB uncorrectable error) doesn't necessarily mean it is a DRAM error.
Remove unused macros while at it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

The fact whether we are chipkill capable or not does not have any
bearing when computing the channel index on a ganged DCT configuration
so remove that. Also, simplify debug statements. Finally, remove old
error injection leftovers, while at it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove family names from macro names, drop single bit defines and
comment their meaning instead.

No functional change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Shorten macro names, remove family name from macros, fix macro
arguments, shorten debug strings.

No functionality change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

* Restrict DCT ganged mode check since only Fam10h supports it
* Adjust DRAM type detection for BD since it only supports DDR3
* Remove second and thus unneeded DCLR read in k8_early_channel_count() - we do
  that in read_mc_regs()
* Cleanup comments and remove family names from register macros
* Remove unused defines

There should be no functional change resulting from this patch.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>