1. 30 10月, 2012 1 次提交
    • M
      ARM: OMAP2+: clockdomain: Fix OMAP4 ISS clk domain to support only SWSUP · 74549de1
      Miguel Vadillo 提交于
      Since CAM domain (ISS) has no module wake-up dependency
      with any other clock domain of the device and the dynamic
      dependency from L3_main_2 is always disabled, the domain
      needs to be in force wakeup in order to be able to access
      it for configure (sysconfig) it or use it.
      
      Also since there is no clock in the domain managed automatically
      by the hardware, there is no use to configure automatic
      clock domain transition. SW should keep the SW_WKUP domain
      transition as long as a module in the domain is required to
      be functional.
      Signed-off-by: NMiguel Vadillo <vadillo@ti.com>
      Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
      74549de1
  2. 24 9月, 2012 1 次提交
    • P
      ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems · b71c7217
      Paul Walmsley 提交于
      The idle status of the IP blocks and clocks inside the EMU clockdomain
      isn't taken into account by the PRCM hardware when deciding whether
      the clockdomain is idle.  Add a workaround flag in the clockdomain
      code, CLKDM_MISSING_IDLE_REPORTING, to deal with this problem, and add
      the code necessary to support it.
      
      If CLKDM_MISSING_IDLE_REPORTING is set on a clockdomain, the
      clockdomain will be forced active whenever an IP block inside that
      clockdomain is in use, even if the clockdomain supports
      hardware-supervised idle.  When the kernel indicates that the last
      active IP block inside the clockdomain is no longer used, the
      clockdomain will be forced idle, or, if that mode is not supported in
      the hardware, it will be placed into hardware-supervised idle.
      
      This patch is an equal collaboration with Jon Hunter
      <jon-hunter@ti.com>.  Ming Lei <ming.lei@canonical.com>, Will Deacon
      <will.deacon@arm.com>, Madhav Vij <mvij@ti.com>, Kevin Hilman
      <khilman@ti.com>, Benoît Cousson <b-cousson@ti.com>, and Santosh
      Shilimkar <santosh.shilimkar@ti.com> all made essential contributions
      to the understanding of EMU clockdomain power management on OMAP.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Jon Hunter <jon-hunter@ti.com>
      Cc: Ming Lei <ming.lei@canonical.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Madhav Vij <mvij@ti.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Cc: Benoît Cousson <b-cousson@ti.com>
      Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
      Tested-by: NJon Hunter <jon-hunter@ti.com>
      b71c7217
  3. 06 7月, 2012 1 次提交
    • P
      ARM: OMAP2+: hwmod code/clockdomain data: fix 32K sync timer · 006c7f18
      Paul Walmsley 提交于
      Kevin discovered that commit c8d82ff6
      ("ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod
      database") broke CORE idle on OMAP3.  This prevents device low power
      states.
      
      The root cause is that the 32K sync timer IP block does not support
      smart-idle mode[1], and so the hwmod code keeps the IP block in
      no-idle mode while it is active.  This in turn prevents the WKUP
      clockdomain from transitioning to idle.  There is a hardcoded sleep
      dependency that prevents the CORE_L3 and CORE_CM clockdomains from
      transitioning to idle when the WKUP clockdomain is active[2], so the
      chip cannot enter any device low power states.
      
      It turns out that there is no need to take the 32k sync timer out of
      idle.  The IP block itself probably does not have any native idle
      handling at all, due to its simplicity.  Furthermore, the PRCM will
      never request target idle for this IP block while the kernel is
      running, due to the sleep dependency that prevents the WKUP
      clockdomain from idling while the CORE_L3 clockdomain is active.  So
      we can safely leave the 32k sync timer in target-force-idle mode, even
      while we continue to access it.
      
      This workaround is implemented by defining a new clockdomain flag,
      CLKDM_ACTIVE_WITH_MPU, that indicates that the clockdomain is
      guaranteed to be active whenever the MPU is inactive.  If an IP
      block's main functional clock exists inside this clockdomain, and the
      IP block does not support smart-idle modes, then the hwmod code will
      place the IP block into target force-idle mode even when enabled.  The
      WKUP clockdomains on OMAP3/4 are marked with this flag.  (On OMAP2xxx,
      no OCP header existed on the 32k sync timer.)   Other clockdomains also
      should be marked with this flag, but those changes are deferred until
      a later merge window, to create a minimal fix.
      
      Another theoretically clean fix for this problem would be to implement
      PM runtime-based control for 32k sync timer accesses.  These PM
      runtime calls would need to located in a custom clocksource, since the
      32k sync timer is currently used as an MMIO clocksource.  But in
      practice, there would be little benefit to doing so; and there would
      be some cost, due to the addition of unnecessary lines of code and the
      additional CPU overhead of the PM runtime and hwmod code - unnecessary
      in this case.
      
      Another possible fix would have been to modify the pm34xx.c code to
      force the IP block idle before entering WFI.  But this would not have
      been an acceptable approach: we are trying to remove this type of
      centralized IP block idle control from the PM code.
      
      This patch is a collaboration between Kevin Hilman <khilman@ti.com>
      and Paul Walmsley <paul@pwsan.com>.
      
      Thanks to Vaibhav Hiremath <hvaibhav@ti.com> for providing comments on
      an earlier version of this patch.  Thanks to Tero Kristo
      <t-kristo@ti.com> for identifying a bug in an earlier version of this
      patch.  Thanks to Benoît Cousson <b-cousson@ti.com> for identifying
      some bugs in several versions of this patch and for implementation
      comments.
      
      References:
      
      1. Table 16-96 "REG_32KSYNCNT_SYSCONFIG" of the OMAP34xx TRM Rev. ZU
         (SWPU223U), available from:
         http://www.ti.com/pdfs/wtbu/OMAP34x_ES3.1.x_PUBLIC_TRM_vzU.zip
      
      2. Table 4-72 "Sleep Dependencies" of the OMAP34xx TRM Rev. ZU
         (SWPU223U)
      
      3. ibid.
      
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Vaibhav Hiremath <hvaibhav@ti.com>
      Cc: Benoît Cousson <b-cousson@ti.com>
      Cc: Tero Kristo <t-kristo@ti.com>
      Tested-by: NKevin Hilman <khilman@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Signed-off-by: NKevin Hilman <khilman@ti.com>
      006c7f18
  4. 20 6月, 2012 1 次提交
  5. 20 4月, 2012 1 次提交
  6. 04 4月, 2012 1 次提交
    • P
      ARM: OMAP44xx: clockdomain data: correct the emu_sys_clkdm CLKTRCTRL data · 7a82ebd9
      Paul Walmsley 提交于
      According to the 4430 ES2.0 TRM vX Table 3-744 "CM_EMU_CLKSTCTRL",
      the emu_sys clockdomain data in mainline is incorrect.
      
      The emu_sys clockdomain does not support the DISABLE_AUTO state, and
      instead it supports the FORCE_WAKEUP state.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Benoît Cousson <b-cousson@ti.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
      Cc: Ming Lei <ming.lei@canonical.com>
      Cc: Will Deacon <will.deacon@arm.com>
      7a82ebd9
  7. 15 9月, 2011 2 次提交
    • P
      OMAP: clockdomain code/data: remove omap_chip bitmask from struct clockdomain · a5ffef6a
      Paul Walmsley 提交于
      At Tony's request, remove the omap_chip bitmasks from the clockdomain
      and clockdomain dependency definitions.  Instead, initialize
      clockdomains based on one or more lists that are applicable to a
      particular SoC family, variant, and silicon revision.
      
      Tony Lindgren <tony@atomide.com> found a bug in a previous version of this
      patch - thanks Tony.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Tony Lindgren <tony@atomide.com>
      a5ffef6a
    • P
      OMAP: clockdomain: split clkdm_init() · 08cb9703
      Paul Walmsley 提交于
      In preparation for OMAP_CHIP() removal, split clkdm_init() into four
      functions.  This allows some of them to be called multiple times: for
      example, clkdm_register_clkdms() can be called once to register
      clockdomains that are common to a group of SoCs, and once to register
      clockdomains that are specific to a single SoC.
      
      The appropriate order to call these functions - which is enforced
      by the code - is:
      
      1. clkdm_register_platform_funcs()
      2. clkdm_register_clkdms() (can be called multiple times)
      3. clkdm_register_autodeps() (optional; deprecated)
      4. clkdm_complete_init()
      
      Convert the OMAP2, 3, and 4 clockdomain init code to use these new
      functions.
      
      While here, improve documentation, and increase CodingStyle
      conformance by shortening some local variable names.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      08cb9703
  8. 10 7月, 2011 2 次提交
    • B
      OMAP4: hwmod data: Add clock domain attribute · a5322c6f
      Benoit Cousson 提交于
      In OMAP PRCM terminology, the clock domain is defined as a group of IPs
      that share some clocks and most of the time an interface clock.
      Every IP does belong to a clockdomain.
      For the moment the clock domain attribute is affected to a clock node.
      The issue with that approach, is that a clock might or not belong to a
      clock domain. Moreover during module transition, it is up to a module
      to handle properly the clock domain state and not to a clock node.
      
      Create a clkdm_name attribute to provide this information per hwmod.
      
      Populate this attribute for every OMAP4 hwmod entries.
      
      Future cleanup series with remove that information from the OMAP4 clock
      when it is relevant.
      Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      [paul@pwsan.com: fix the mpuss_clkdm name]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      a5322c6f
    • B
      OMAP4: clockdomain data: Fix data order and wrong name · 3c95b707
      Benoit Cousson 提交于
      MPUSS was renamed MPU and L3_D2D D2D.
      The rename will slightly change the order of the structure
      and thus generate some structures moves.
      
      Add a comment and remove a comma.
      
      Update Copyright for TI and Nokia and add back Paul
      in the author list.
      Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      3c95b707
  9. 02 3月, 2011 1 次提交
  10. 26 2月, 2011 3 次提交
  11. 19 1月, 2011 1 次提交
    • F
      OMAP: PRCM: remove duplicated headers · bc9fcaf3
      Felipe Balbi 提交于
      A few headers are included twice, remove them.
      
      Found the following errors using make includecheck:
      arch/arm/mach-omap2/clock44xx_data.c: prm44xx.h is
      included more than once.
      arch/arm/mach-omap2/clockdomains44xx_data.c: cm1_44xx.h
      is included more than once.
      arch/arm/mach-omap2/clockdomains44xx_data.c: cm2_44xx.h
      is included more than once.
      arch/arm/mach-omap2/powerdomain2xxx_3xxx.c: prm-regbits-34xx.h
      is included more than once.
      
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      [paul@pwsan.com: dropped lists from patch cc:s; tweaked subject line]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      bc9fcaf3
  12. 22 12月, 2010 5 次提交
  13. 21 5月, 2010 1 次提交
  14. 27 1月, 2010 3 次提交