1. 15 6月, 2016 1 次提交
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      ASoC: adau17x1: Add support for specifying the MCLK using the CCF · 5d76de61
      Lars-Peter Clausen 提交于
      The devices from the ADAU17X1 family all have a MCLK clock input which
      supplies the master clock for the device. The master clock is used as the
      input clock for the PLL. Currently the MCLK rate as well as the desired PLL
      output frequency need to be supplied by calling snd_soc_dai_set_pll() form
      a machine driver.
      
      Add support for specifying the MCLK using the common clock framework. In
      addition to that also automatically configure the PLL to a suitable rate
      if the master clock was provided using the CCW. This allows to use the
      CODEC driver without any special configuration requirements from the
      machine driver.
      
      While the PLL output frequency can be configured over a (more or less)
      continuous range the narrowness of the range and the other constraints of
      the clocking tree usually only result in two output frequencies that will
      actually be chosen. One for 44.1kHz based rates and one for 48kHz based
      rates, these are the rates that the automatic PLL configuration will use.
      For the rare case where a non-standard setup is required a machine driver
      can disable the auto-configuration and configure a custom frequency using
      the existing mechanisms.
      
      If the common clock framework is not enabled clk_get() will return NULL and
      the driver will function as before and the clock rate needs to be
      configured manually.
      Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      5d76de61
  2. 10 6月, 2016 1 次提交
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      ASoC: adau: Factor out shared PLL configuration code · 0eadaa9c
      Lars-Peter Clausen 提交于
      Multiple devices from the ADAU family share the same PLL structure and
      configuration register layout. Introduce a new helper module that can be
      used to calculated the PLL configuration registers based on a specified
      input frequency and the desired output frequency of the PLL.
      
      The ADAU1761/ADAU1781 and ADAU1373 drivers are updated to make use of this
      new helper module. But future drivers for additional devices from the ADAU
      family are also expected to make use of it.
      
      In anticipation of sharing more infrastructure code between different
      devices from the ADAU family the new module is called adau-utils.
      Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      0eadaa9c
  3. 05 5月, 2015 1 次提交
  4. 22 11月, 2014 1 次提交
  5. 20 11月, 2014 1 次提交
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      ASoC: sigmadsp: Restructure in preparation for fw v2 support · d48b088e
      Lars-Peter Clausen 提交于
      The v2 file format of the SigmaDSP takes a more declarative style compared
      to the imperative style of the v1 format. In addition some features that are
      supported with v2 require the driver to keep state around for the firmware.
      This requires a bit of restructuring of both the firmware loader itself and
      the drivers making use of the firmware loader.
      
      Instead of loading and executing the firmware in place when the DSP is
      configured the firmware is now loaded at driver probe time. This is required
      since the new firmware format will in addition to the firmware data itself
      contain meta information describing the firmware and its requirements and
      capabilities. Those will for example be used to restrict the supported
      samplerates advertised by the driver to userspace to the list of samplerates
      supported for the firmware.
      
      This only does the restructuring required by the v2 format, but does not
      yet add support for the new format itself.
      Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      d48b088e
  6. 17 11月, 2014 1 次提交
  7. 05 9月, 2014 1 次提交
  8. 31 7月, 2014 1 次提交
  9. 28 5月, 2014 1 次提交