xdma_event_intr1.clkout2 pad can be used to source clock
from either 32K OSC or any of the PLL (except MPU) outputs.
On the existing AM335x based boards (EVM, EVM-SK and Bone),
this pad is used to feed the clock to audio codes.

So, this patch configures the pinmux to get clkout2 on the pad.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Add pin control binding for UART0 device nodes in all
board specific DT files.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Acked-by: NMatt Porter <mporter@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

With DT support, where naming convention is based on base-addr
and not id, so we should follow TRM/Spec numbering label.

This patch changes UART numbering as per TRM, as uart0-5.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Acked-by: NMatt Porter <mporter@ti.com>
Cc: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Now gpio-leds driver is using devm_pinctrl_get_select_default()
api to set default pinmux configuration required for the
functionality of the driver, so this patch moves respective
pinctrl binding inside leds node.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Add pin control binding for I2C device nodes in all
board specific DT files (as per current usage),

EVM: Both i2c0 and i2c1
EVM-SK and Bone: Only i2c0
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Acked-by: NMatt Porter <mporter@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

The carveouts that have been reserved for multimedia usecases
are not being used currently by any driver and so have been
cleaned up. Memory will be allocated runtime through CMA for
enabling the multimedia usecases.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

The ranges DT entry needed by the PCIe controller is defined at the
SoC .dtsi level. However, some boards have a NOR flash, and to support
it, they need to override the SoC-level ranges property to add an
additional range. Since PCIe and NOR support came separately, some
boards were not properly changed to include the PCIe range in their
ranges property at the .dts level.

This commit fixes those platforms.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The previous mask values for the legacy ARM CPU IDs were conflicting
with the CPU ID assignments for late-generation CPUs (like the
Qualcomm MSM/QSD or Broadcom Brahma-15 processors). This change
corrects the legacy ARM CPU ID value so that the jump table can
fall-through to the appropriate cache maintenance / MMU functions.
Signed-off-by: NMarc C <marc.ceeeee@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

In August 2012, Matthew Gretton-Dann checked a change into binutils
labelled "Error on obsolete & warn on deprecated registers", apparently as
part of ARMv8 support. Apparently, this was supposed to emit the message
"Warning: This coprocessor register access is deprecated in ARMv8" when
using certain mcr/mrc instructions and building for ARMv8. Unfortunately,
the message that is actually emitted appears to be '(null)', which is
less helpful in comparison.

Even more unfortunately, this is biting us on every single kernel
build with a new gas, because arch/arm/boot/compressed/head.S and some
other files in that directory are built with -march=all since kernel
commit 80cec14a "[ARM] Add -march=all to assembly file build in
arch/arm/boot/compressed" back in v2.6.28.

This patch reverts Russell's nice solution and instead marks the head.S
file to be built for armv7-a, which fortunately lets us build all
instructions in that file without warnings even on the broken binutils.

Without this patch, building anything results in:

arch/arm/boot/compressed/head.S: Assembler messages:
arch/arm/boot/compressed/head.S:565: Warning: (null)
arch/arm/boot/compressed/head.S:676: Warning: (null)
arch/arm/boot/compressed/head.S:698: Warning: (null)
arch/arm/boot/compressed/head.S:722: Warning: (null)
arch/arm/boot/compressed/head.S:726: Warning: (null)
arch/arm/boot/compressed/head.S:957: Warning: (null)
arch/arm/boot/compressed/head.S:996: Warning: (null)
arch/arm/boot/compressed/head.S:997: Warning: (null)
arch/arm/boot/compressed/head.S:1027: Warning: (null)
arch/arm/boot/compressed/head.S:1035: Warning: (null)
arch/arm/boot/compressed/head.S:1046: Warning: (null)
arch/arm/boot/compressed/head.S:1060: Warning: (null)
arch/arm/boot/compressed/head.S:1092: Warning: (null)
arch/arm/boot/compressed/head.S:1094: Warning: (null)
arch/arm/boot/compressed/head.S:1095: Warning: (null)
arch/arm/boot/compressed/head.S:1102: Warning: (null)
arch/arm/boot/compressed/head.S:1134: Warning: (null)
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: stable@vger.kernel.org
Cc: Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Selecting this option produces:

  AS      arch/arm/boot/compressed/debug.o
arch/arm/boot/compressed/debug.S:4:33: fatal error: mach/debug-macro.S: No such file or directory
compilation terminated.
make[3]: *** [arch/arm/boot/compressed/debug.o] Error 1

The semihosting support cannot be modelled into a senduart macro as
it requires memory space for argument passing.  So the
CONFIG_DEBUG_LL_INCLUDE may not have any sensible value and the include
directive should be omitted.

While at it, let's add proper semihosting output support to the
decompressor.
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

OMAP5 has 6 timers (GPTimers 5, 6, 8 to 11) that are capable of PWM.
The PWM capability property is missing from the node definitions of
couple of timers.

Add ti,timer-pwm attribute for timer 5, 6, 8 and 11.
Signed-off-by: NSuman Anna <s-anna@ti.com>
[benoit.cousson@linaro.org: Update changelog and subject to highlight
the fix]
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Earlier commits ensured proper muxing of pins related to proper
TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure
sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM:
OMAP4: TWL: mux sys_drm_msecure as output for PMIC).

However these only fixed legacy boot and not DT boot.  For DT boot,
the default mux values need to be set properly in DT.

Special thanks to Nishanth Menon for the review and catching some
major flaws in earlier versions.

Tested on OMAP4430/Panda and OMAP4460/Panda-ES.

Cc: Nishanth Menon <nm@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>
Acked-by: NGrygorii Strashko <grygorii.strashko@ti.com>
[benoit.cousson@linaro.org: Slightly change the subject to align
board name with file name]
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

The gpmc driver is actually looking for "gpmc,num-cs" and
"gpmc,num-waitpins" properties in DT. The binding doc also states
this.
Correct the properties in the dts to provide the right values for the
gpmc driver.
Signed-off-by: NLars Poeschel <poeschel@lemonage.de>
Acked-by: NPeter Korsgaard <jacmet@sunsite.dk>
Acked-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Stephen Warren reported the recent commit 78506f22 (add support for
extended FIFO-size of PL011-r1p5) breaks the serial port on the
BCM2835 ARM SoC.

A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs.
The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep
FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for
this compatibility issue, this patch overrides the HW UART periphid
register values with the actually compatible UART periphid 0x00241011
(r1p3 or r1p4).
Reported-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NJongsung Kim <neidhard.kim@lge.com>
Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The PA24 pin is wrongly assigned to peripheral B.
In the current config there is 2 ETX3 pins (PA11 and PA24) and
no ETXER pin (PA22).
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Cc: stable <stable@vger.kernel.org> # 3.8+

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The CSPI controller has only one clock, but the driver spi-imx.c needs
clock "per" to calculate bitrate divisor.
Signed-off-by: NJonas Andersson <jonas@microbit.se>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The assignment of IRQ for the SMC91x ethernet adapter had two
problems making it non-working:

- It was not put into the ethernet device node. Let's do this
  by using the board-specific overlay, so we can make other
  overlays on other Nomadik boards.

- The IRQ number was actually completely wrong, this was the
  number for NHK8815, not S8815.

After this ethernet starts working on the USB S8815.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

During the conversion to the internal-regs' subnode, the L2-cache node
haven not been converted (due to a wrong choice made by myself during
the resolution of the merge conflict when I rebased the commit). This
leads to wrong address for L2 cache which prevent it to be used on
Armada 370. This commit fix the address reg of the e L2-cache node.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Adding usbphy node for Exynos5250 along with the
necessary device data to be parsed.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Since 82a68267 ('ARM: dts: mvebu: Convert all the mvebu files to use
the range property') all the device nodes of Armada 370/XP are under a
common 'ranges' property that translates the device register addresses
into their absolute address, thanks to the base address of the
internal register space.

However, beyond just the register areas, there are also PCIe I/O and
memory regions, whose addresses should be properly translated. This
patch fixes the Armada 370 and XP ranges property to take PCIe into
account properly.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

With the latest device tree reorganization which introduced the
'internal-reg' node, now the only region translated is the internal register's.
This makes the description of the hardware incomplete, for it lacks the
Device Bus childs address space.

In order to fix this, it's required to add a 'ranges' entry with a suitable
address space to map Device Bus childs, on a per-board basis.
This patch fixes the ranges property on the Armada XP GP board.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Commit ad871c10 (ARM: dts: OMAP: Add usb_otg and glue data to
OMAP3+ boards) added support for MUSB on omap3 for device tree,
but added the interrupts the wrong way probably as they were
copied from the omap4.dtsi file. On omap3 we have TI specific
interrupt controller, not GIC.

Fix this by specifying the interrupt following the TI INTC
binding.

Without this fix MUSB won't work as it is trying to use
irq0 instead of irq92.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Instead of requesting all available spi cs-gpios, request only the ones used on
the board, in our case on the cpu module.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Cc: stable <stable@vger.kernel.org> # 3.8+

With the latest device tree reorganization which introduced the
'internal-reg' node, now the only region translated is the internal register's.
This makes the description of the hardware incomplete, for it lacks the
Device Bus childs address space.

In order to fix this, it's required to add a 'ranges' entry with a suitable
address space to map Device Bus childs, on a per-board basis.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The mpic alias is already defined in the common armada-370-xp.dtsi, so
there's no need to repeat it at the armada-xp.dtsi and armada-370.dtsi
level.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Commit b00adbe0 ("ARM: sunxi: Rename uart nodes to serial") changed the
node names in the DTSI, changes that were not accordingly made to the
Mini X-Plus device tree. This breakage slipped through because it was
not properly declared in the Makefile.

Fix both issues.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The 'samsung,vbus-gpio' was submitted before pinmux landed for
exynos5250 and uses the old-style gpio specifier.  Fix the two
exynos5250 boards that use it.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Trivial patch, adding the i2c Cypress trackpad used on Snow.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>

If a board isn't using twl4030, then dtc will complain about the missing
phandle (which is in twl4030.dtsi).  Move the phy declaration to the dts
files.
Signed-off-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The bootloader configures the pins, but has pull bits
set without pull enable bits. While this is harmless,
and won't do anything, it seems to cause confusion at
least for me every time looking at the pin configuration.
Fix it for DT based boot.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add GPMC data node to AM33XX device tree file.
Signed-off-by: NPhilip Avinash <avinashphilip@ti.com>
Acked-by: NPeter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

commit d16fb25d (ARM: dts: OMAP4460: Add CPU OPP table)
introduced wrong OPP voltages per OPP by mistake. Sync the OPP
tables with existing OMAP4460 OPP data in
arch/arm/mach-omap2/opp4xxx_data.c
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

commit 3027e267 (ARM: dts: OMAP36xx: Add CPU OPP table)
introduced wrong OPP voltages per OPP by mistake. Sync the OPP
tables with existing OMAP36xx OPP data in
arch/arm/mach-omap2/opp3xxx_data.c
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Commit ff5c9059 (ARM: dts: OMAP3+: Correct gpio #interrupts-cells
property) updated the number of interrupt cells required for configuring
gpios as interrupts for other devices (such as ethernet controllers).
This update allowed the interrupt type (edge, level, etc) to be
configured via device-tree (as described in the
Documentation/devicetree/bindings/gpio/gpio-omap.txt).

This broke ethernet support on the OMAP4 SDP board that defines a gpio
as the ethernet IRQ because the interrupt type (level, edge, etc) was
not getting configured correctly. This board use the ks8851 ethernet
chip which has an active low interrupt. Fix this by defining the gpio
interrupt as active-low in the device-tree binding.

Please note that the OMAP4-VAR-SOM also uses the same ethernet
controller and it is expected it will have the same problem. So the
same fix is also applied to this board.
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

I fumbled when resolving a merge conflict on application of commit
765d012c (ARM: dts: exynos4210: Add basic dts file for universal_c210
board), and left out the dts source file. Here it is.
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds basic device tree sources for Universal C210 board.

Currently support includes:
- eMMC
- serial
- max8952 and max8998 voltage regulators.
- gpio-keys

More support will be added in further patches.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds device tree node for PWM block present on Exynos 4 SoCs.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>